3_08bcu

大型risc处理器设计源代码,这是书中的代码 基于流水线的risc cpu设计

  //                                                                             g0128
  // RESET, initialize bus protocols                                             g0129
  //                                                                             g0130
  always @(nRESET) begin                                                         g0131
    while (~nRESET) begin                                                        g0132
      ACC_MODE = 3'b111; // RESET state (FACC=1, ACMD=11)                        g0133
      ABP_ADDE = 0;      // disable address output (asynchronous)                g0134
      ABP_BUSY = 0;      // disable (asynchronous)                               g0135
      ABP_DADE = 0;      // disable data output (asynchronous)                   g0136
      ABP_READ = 0;      // disable read access (asynchronous)                   g0137
      ABP_RnW  = 1;      // RnW (asynchronous)                                   g0138
      ABP_nMRQ = 1;      // nMRQ (asynchronous)                                  g0139
      ABP_nRMW = 1;      // nRMW (asynchronous)                                  g0140
      SBP_ADDE = 0;      // disable address output (synchronous)                 g0141
      SBP_BUSY = 0;      // disable (synchronous)                                g0142
      SBP_DADE = 0;      // disable data output (synchronous)                    g0143
      SBP_READ = 0;      // disable read access (synchronous)                    g0144
      SBP_RnW  = 1;      // RnW (synchronous)                                    g0145
      SBP_SWAP = 0;      // no SWAP access (synchronous)                         g0146
      SBP_nMRQ = 1;      // nMRQ (synchronous)                                   g0147
      SBP_nRMW = 1;      // nRMW (synchronous)                                   g0148
      #1;                                                                        g0149
    end                                                                          g0150
  end                                                                            g0151
                                                                                 g0152
  //                                                                             g0153
  // Save BCU_ACC_MODE                                                           g0154
  //                                                                             g0155
  always @(posedge CP) begin                                                     g0156
    if (nRESET & BCU_READY) begin                                                g0157
        ACC_MODE = #`DELTA BCU_ACC_MODE;                                         g0158
    end                                                                          g0159
  end                                                                            g0160
                                                                                 g0161
  //                                                                             g0162
  // Drive address bus                                                           g0163
  //                                                                             g0164
  always @(BUS_PRO or ABP_ADDE or SBP_ADDE or                                    g0165
           ACC_MODE or MAU_ADDR_BUS or IFU_ADDR_BUS) begin                       g0166
    casez({BUS_PRO, ABP_ADDE, SBP_ADDE, ACC_MODE[2]})                            g0167
      4'b01?0: ADDR_DRV = MAU_ADDR_BUS;           // MAU access (asynchronous)   g0168
      4'b01?1: ADDR_DRV = {IFU_ADDR_BUS, 2'b00};  // IFU access (asynchronous)   g0169
      4'b1?10: ADDR_DRV = MAU_ADDR_BUS;           // MAU access (synchronous)    g0170
      4'b1?11: ADDR_DRV = {IFU_ADDR_BUS, 2'b00};  // IFU access (synchronous)    g0171
      default: ADDR_DRV = 32'bz;                  // no access                   g0172
    endcase                                                                      g0173
  end                                                                            g0174
                                                                                 g0175
  //                                                                             g0176
  // Drive data bus                                                              g0177
  //                                                                             g0178
  always @(BUS_PRO or RnW or ACC_MODE or                                         g0179
           ABP_DADE or SBP_DADE or MAU_ADDR_BUS) begin                           g0180
    if ((~BUS_PRO & ABP_DADE) | (BUS_PRO & SBP_DADE)) begin                      g0181
      casez({RnW, ACC_MODE[1:0], MAU_ADDR_BUS[1:0]})                             g0182
        5'b010??: begin                                      // word data        g0183
                    DATA_DRV[31:0] = MAU_WRITE_DATA[31:0];   // write            g0184
                  end                                                            g0185
        5'b0010?: begin                                      // halfword data    g0186
                    DATA_DRV[31:16] = 16'bz;                 // write            g0187
                    DATA_DRV[15: 0] = MAU_WRITE_DATA[15: 0]; // (alignment=00)   g0188
                  end                                                            g0189
        5'b0011?: begin                                      // halfword data    g0190
                    DATA_DRV[31:16] = MAU_WRITE_DATA[31:16]; // write            g0191
                    DATA_DRV[15: 0] = 16'bz;                 // (alignment=10)   g0192
                  end                                                            g0193
        5'b00000: begin                                      // byte data        g0194
                    DATA_DRV[31: 8] = 24'bz;                 // write            g0195
                    DATA_DRV[ 7: 0] = MAU_WRITE_DATA[ 7: 0]; // (alignment=00)   g0196
                  end                                                            g0197
        5'b00001: begin                                      // byte data        g0198
                    DATA_DRV[31:16] = 16'bz;                 // write            g0199
                    DATA_DRV[15: 8] = MAU_WRITE_DATA[15: 8]; // (alignment=01)   g0200
                    DATA_DRV[ 7: 0] = 8'bz;                                      g0201
                  end                                                            g0202
        5'b00010: begin                                      // byte data        g0203
                    DATA_DRV[31:24] = 8'bz;                  // write            g0204
                    DATA_DRV[23:16] = MAU_WRITE_DATA[23:16]; // (alignment=10)   g0205
                    DATA_DRV[15: 0] = 16'bz;                                     g0206
                  end                                                            g0207
        5'b00011: begin                                      // byte data        g0208
                   DATA_DRV[31:24] = MAU_WRITE_DATA[31:24];  // write            g0209
                   DATA_DRV[23: 0] = 24'bz;                  // (alignment=11)   g0210
                  end                                                            g0211
        default:  DATA_DRV = 32'bz;                          // read access      g0212
      endcase                                                                    g0213
    end                                                                          g0214
    else DATA_DRV = 32'bz;                                   // no access        g0215
  end                                                                            g0216
                                                                                 g0217
  //                                                                             g0218
  // Read data from data bus                                                     g0219
  //                                                                             g0220
  always @(BUS_PRO or ABP_READ or SBP_READ or DATA_BUS) begin                    g0221
    casez({BUS_PRO, ABP_READ, SBP_READ})                                         g0222
      3'b01?: READ_BUFFER = DATA_BUS;     // asynchronous                        g0223
      3'b1?1: READ_BUFFER = DATA_BUS;     // synchronous                         g0224
    endcase                                                                      g0225
  end                                                                            g0226
                                                                                 g0227
  //------------------------------------------------------------------------     g0228
  //                                                                             g0229
  // Asynchronous bus protocol                                                   g0230
  //                                                                             g0231
  //------------------------------------------------------------------------     g0232
                                                                                 g0233
  //                                                                             g0234
  // New memory access                                                           g0235
  //                                                                             g0236
  always @(posedge CP) begin                                                     g0237
    if (~ABP_BUSY & nRESET & (DO_FETCH | ~BCU_ACC_MODE[2])) begin                g0238
      fork                                                                       g0239
        ABP_ADDE = #`DELTA 1;      // enable address output                      g0240
        ABP_BUSY = #`DELTA 1;      // note begin of access                       g0241
        ABP_RnW  = #`DELTA BCU_ACC_DIR[1] | ~BCU_ACC_DIR[0]; // set RnW          g0242
        ABP_nRMW = #`DELTA ~BCU_ACC_DIR[1];                  // set nRMW         g0243
        ABP_nMRQ = #`BCUDELAY 0;   // output memory request to memory            g0244
      join                                                                       g0245
    end                                                                          g0246
  end                                                                            g0247
                                                                                 g0248
  //                                                                             g0249
  // Memory access                                                               g0250
  //                                                                             g0251
  always @(negedge nMHS) begin                                                   g0252
    if (ABP_BUSY & nRESET) begin                                                 g0253
      if (RnW) begin                                                             g0254
        ABP_READ = 1;     // read data                                           g0255