3_01chip

大型risc处理器设计源代码,这是书中的代码 基于流水线的risc cpu设计

//  WORK_IF:         0: no memory access                                         p0128
//                   1: load instruction                                         p0129
//  WORK_MA:         0: hold input register                                      p0130
//                   1: load input register                                      p0131
//  STEP:            0: hold pipeline (long memory access)                       p0132
//                   1: shift pipeline                                           p0133
//  WORK_WB:         0: hold input register                                      p0134
//                   1: load input register                                      p0135
//  USE_IMMEDIATE:   0: IMMEDIATE invalid                                        p0136
//                   1: IMMEDIATE valid                                          p0137
//  USE_PCU_PC:      0: ignore PC_BUS address                                    p0138
//                   1: use PC_BUS address                                       p0139
//  USE_SREG_DATA:   0: SREG_DATA invalid                                        p0140
//                   1: SREG_DATA valid                                          p0141
//----------------------------------------------------------------------------   p0142
                                                                                 p0143
module chip (                                                                    p0144
    ADDR_BUS,                                                                    p0145
    ACC_MODE, nIRA, RnW, nRMW, nMRQ, FACC, KU_MODE,                              p0146
    DATA_BUS,                                                                    p0147
    CONFIG, IRQ_ID, CP, nRESET, nIRQ, nMHS, nHLT, BUS_PRO                        p0148
  );                                                                             p0149
                                                                                 p0150
  //  Port declarations for 'external connections' ("pins")                      p0151
  output [31:0] ADDR_BUS;       // output system address bus                     p0152
  output [ 1:0] ACC_MODE;       // output access mode                            p0153
  output        nIRA,           // output interrupt acknowledge                  p0154
                RnW,            // output memory read write                      p0155
                nRMW,           // output read modify write                      p0156
                nMRQ,           // output memory request                         p0157
                FACC,           // output fetch access                           p0158
                KU_MODE;        // output kernel/user mode                       p0159
  inout  [31:0] DATA_BUS;       // input/output system data bus                  p0160
  input  [ 4:0] CONFIG;         // input cache configuration                     p0161
  input  [ 2:0] IRQ_ID;         // input interrupt identification                p0162
  input         CP,             // input system clock                            p0163
                nRESET,         // input reset                                   p0164
                nIRQ,           // input interrupt request                       p0165
                nMHS,           // input memory handshake                        p0166
                nHLT,           // input halt signal                             p0167
                BUS_PRO;        // input bus protocol                            p0168
                                                                                 p0169
  //  Wire declarations for 'external connections' ("pins")                      p0170
  wire   [31:0] ADDR_BUS;       // system address bus                            p0171
  wire   [ 1:0] ACC_MODE;       // access mode                                   p0172
  wire          nIRA,           // interrupt acknowledge                         p0173
                RnW,            // memory read write                             p0174
                nRMW,           // read modify write                             p0175
                nMRQ,           // memory request                                p0176
                FACC,           // fetch access                                  p0177
                KU_MODE;        // kernel/user mode                              p0178
  wire   [31:0] DATA_BUS;       // system data bus                               p0179
  wire   [ 4:0] CONFIG;         // cache configuration                           p0180
  wire   [ 2:0] IRQ_ID;         // interrupt identification                      p0181
  wire          CP,             // system clock                                  p0182
                nRESET,         // reset                                         p0183
                nIRQ,           // interrupt request                             p0184
                nMHS,           // memory handshake                              p0185
                nHLT,           // halt signal                                   p0186
                BUS_PRO;        // bus protocol                                  p0187
                                                                                 p0188
  // Declarations for 'internal connections' (data)                              p0189
  wire [31:0] A_BUS,            // operand bus A                                 p0190
              B_BUS,            // operand bus B                                 p0191
              C3_BUS,           // ALU result                                    p0192
              C4_BUS,           // MAU result                                    p0193
              I_BUS,            // instruction bus                               p0194
              IFU_DATA_BUS,     // instruction data read                         p0195
              IMMEDIATE,        // immediate operand                             p0196
              MAU_READ_DATA,    // memory access data read                       p0197
              MAU_WRITE_DATA,   // memory access data to be written              p0198
              SREG_DATA,        // special register data read                    p0199
              D_BUS;            // source of data to be written                  p0200
  wire [ 3:0] ALU_OPCODE,       // ALU opcode                                    p0201
              FLAGS_FROM_ALU,   // result flags of ALU                           p0202
              IF_FLAGS,         // flags for IF branch decision                  p0203
              FD_FLAGS,         // flags for FD branch decision                  p0204
              SWI_ID;           // software interrupt ID                         p0205
  wire [ 2:0] BCU_ACC_MODE,     // BCU access mode                               p0206
              EXCEPT_ID,        // exception ID                                  p0207
              MAU_ACC_MODE2,    // MAU access mode (ID stage)                    p0208
              MAU_ACC_MODE3,    // MAU access mode (EX stage)                    p0209
              MAU_OPCODE2,      // MAU opcode (ID stage)                         p0210
              MAU_OPCODE3;      // MAU opcode (EX stage)                         p0211
  wire [ 1:0] BCU_ACC_DIR,      // BCU access direction                          p0212
              INT_STATE;        // register file interrupt state                 p0213
  wire        ALU_CARRY;        // carry operand                                 p0214
                                                                                 p0215
  // Declarations for 'internal connections' (addresses)                         p0216
  wire [31:0] MAU_ADDR_BUS;     // address for memory access data                p0217
  wire [31:2] IFU_ADDR_BUS,     // address of next instruction >> 2              p0218
              NPC_BUS,          // (present instruction address +4) >> 2         p0219
              PC_BUS;           // PC bus                                        p0220
  wire [ 4:0] ADDR_A,           // address of register operand A                 p0221
              ADDR_B,           // address of register operand B                 p0222
              ADDR_C,           // address for destination register              p0223
              ADDR_D;           // address for write data register               p0224
  wire [ 3:0] SREG_ADDR;        // special register address                      p0225
                                                                                 p0226
  // Declarations for 'internal connections' (control signals)                   p0227
  wire        BCU_READY,        // memory access status                          p0228
              BREAK_MEM_ACC,    // memory access interrupt request               p0229
              CALL_NOW,         // CALL                                          p0230
              CCLR,             // clear cache                                   p0231
              DIS_ALU,          // ALU deactivation request                      p0232
              DIS_IDU,          // IDU deactivation request                      p0233
              DO_HALT,          // HALT                                          p0234
              DO_RETI,          // RETI                                          p0235
              DS_IN_IFU,        // IFU delay slot                                p0236
              EMERG_FETCH,      // first instruction of interrupt                p0237
              EXCEPT_CTR,       // 'Delayed CTR' exception request               p0238
              EXCEPT_RQ,        // exception request                             p0239
              ID_KU_MODE,       // kernel/user mode of ID stage                  p0240
              IF_KU_MODE,       // kernel/user mode of IF stage                  p0241
              IFU_CORRECT,      // branch correction                             p0242
              IFU_FETCH_RQ,     // instruction access request                    p0243
              KILL_IDU,         // deactivate IDU                                p0244
              LDST_ACC_NOW,     // MAU bus access                                p0245
              NEW_FLAGS,        // ALU.F                                         p0246
              SREG_ACC_DIR,     // special register access direction             p0247
              SWI_RQ,           // software interrupt request                    p0248
              USE_IMMEDIATE,    // IMMEDIATE                                     p0249
              USE_PCU_PC,       // PC_BUS                                        p0250
              USE_SREG_DATA,    // SREG_DATA                                     p0251
              WORK_EX,          // enable EX stage                               p0252
              WORK_FD,          // enable FD stage                               p0253
              WORK_ID,          // enable ID stage                               p0254
              WORK_IF,          // enable IF stage                               p0255