3_05mau

大型risc处理器设计源代码,这是书中的代码 基于流水线的risc cpu设计

//----------------------------------------------------------------------------   d0000
//                                                                               d0001
// MAU: module of memory access unit                                             d0002
//                                                                               d0003
// This module accesses the memory and transfers read data from                  d0004
// MAU_READ_DATA to C4_BUS and data to be written from D_BUS                     d0005
// to MAU_WRITE_DATA. Access modes BYTE and DBYTE are handled                    d0006
// by selecting appropriate bit positions, and the sign of                       d0007
// read data is extended when necessary.                                         d0008
//                                                                               d0009
// Selections of bit positions use the                                           d0010
// access address at the MAU_ADDR_BUS.                                           d0011
//                                                                               d0012
// If there is no memory access, the data from C3_BUS                            d0013
// are buffered and transfered to C4_BUS.                                        d0014
//                                                                               d0015
// With work enable at the rising clock edge (WORK_MA =1),                       d0016
// the data of C3_BUS and D_BUS as well as access mode and                       d0017
// access opcode are taken into input registers, before                          d0018
// they are computed further.                                                    d0019
//                                                                               d0020
// The data of MAU_READ_DATA are taken asynchronously.                           d0021
//                                                                               d0022
// Operations:                                                                   d0023
//   3'b000: load data                                                           d0024
//   3'b001: load data and extend sign                                           d0025
//   3'b010: store data                                                          d0026
//   3'b011: exchange data (SWAP)                                                d0027
//   3'b1XX: transfer data from C3 to C4 unchanged                               d0028
//                                                                               d0029
// Access modes for load and store instructions:                                 d0030
//   3'b0XX: byte access                                                         d0031
//   3'b1X0: halfword access                                                     d0032
//   3'b1X1: word access                                                         d0033
//                                                                               d0034
//----------------------------------------------------------------------------   d0035
                                                                                 d0036
module mau (                                                                     d0037
    C4_BUS, MAU_WRITE_DATA,                                                      d0038
    MAU_ADDR_BUS,                                                                d0039
    D_BUS, MAU_READ_DATA,                                                        d0040
    C3_BUS,                                                                      d0041
    MAU_ACC_MODE_3, MAU_OPCODE_3,                                                d0042
    CP, WORK_MA                                                                  d0043
  );                                                                             d0044
                                                                                 d0045
  // Outputs                                                                     d0046
  output [31:0] C4_BUS,         // data bus C4                                   d0047
                MAU_WRITE_DATA, // BCU write data                                d0048
                MAU_ADDR_BUS;   // access address                                d0049
                                                                                 d0050
  // Inputs                                                                      d0051
  input  [31:0] D_BUS,          // data to be written                            d0052
                MAU_READ_DATA,  // BCU read data                                 d0053
                C3_BUS;         // data bus C3                                   d0054
  input  [ 2:0] MAU_ACC_MODE_3, // access mode                                   d0055
                MAU_OPCODE_3;   // opcode                                        d0056
  input         CP,             // system clock                                  d0057
                WORK_MA;        // work enable                                   d0058
                                                                                 d0059
  reg    [31:0] C4_BUS,         // output register for C4_BUS                    d0060
                MAU_WRITE_DATA, // output register for MAU_WRITE_DATA            d0061
                MAU_ADDR_BUS;   // output register for MAU_ADDR_BUS              d0062
  wire   [31:0] D_BUS,          // data to be written                            d0063
                MAU_READ_DATA,  // BCU read data                                 d0064
                C3_BUS;         // data bus C3                                   d0065
  wire   [ 2:0] MAU_ACC_MODE_3, // access mode                                   d0066
                MAU_OPCODE_3;   // opcode                                        d0067
  wire          CP,             // system clock                                  d0068
                WORK_MA;        // work enable                                   d0069
                                                                                 d0070
  reg    [31:0] MAU_C3REG,      // input register for C3_BUS                     d0071
                MAU_DBREG,      // input register for D_BUS                      d0072
                ST_MAPP16,      // write data selected by halfword               d0073
                ST_MAPP08,      // write data selected by byte                   d0074
                LD_MAPP16,      // read data selected by halfword                d0075
                LD_MAPP08,      // read data selected by byte                    d0076
                FILTERED,       // read data filtered                            d0077
                SIGNMASK;       // sign extension mask                           d0078
  reg    [ 2:0] MAU_AMREG,      // input register for MAU_ACC_MODE_3             d0079
                MAU_OPREG;      // input register for MAU_OPCODE_3               d0080
  reg    [ 1:0] ACCSIZ,         // access width                                  d0081
                MAPPING;        // selection for data                            d0082
                                                                                 d0083
  //                                                                             d0084
  // Read inputs with rising clock edge,                                         d0085
  // if work enable                                                              d0086
  //                                                                             d0087
  always @(posedge CP) begin                                                     d0088
    if (WORK_MA) begin                                                           d0089
      fork                                                                       d0090
        MAU_C3REG = #`DELTA C3_BUS;                                              d0091
        MAU_DBREG = #`DELTA D_BUS;                                               d0092
        MAU_AMREG = #`DELTA MAU_ACC_MODE_3;                                      d0093
        MAU_OPREG = #`DELTA MAU_OPCODE_3;                                        d0094
      join                                                                       d0095
    end                                                                          d0096
  end                                                                            d0097
                                                                                 d0098
  //                                                                             d0099
  // Update MAU_ADDR_BUS                                                         d0100
  //                                                                             d0101
  always @(MAU_C3REG)                                                            d0102
    MAU_ADDR_BUS = MAU_C3REG;                                                    d0103
                                                                                 d0104
  //                                                                             d0105
  // Access width                                                                d0106
  // ACCSIZ: 00: swap, read, or write access to a word                           d0107
  //         01: read or write access to a byte                                  d0108
  //         10: read or write access to a halfword                              d0109
  //                                                                             d0110
  always @(MAU_OPREG or MAU_AMREG) begin                                         d0111
    ACCSIZ[0] = ~(&MAU_OPREG[1:0]) & ~MAU_AMREG[2];                              d0112
    ACCSIZ[1] = ~(&MAU_OPREG[1:0]) & ~MAU_AMREG[0] & MAU_AMREG[2];               d0113
  end                                                                            d0114