📄 3_02ifu
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LAST_USE_PCU_PC, // use delayed external PC a0149
CLR_BTC, // clear BTC a0150
CLR_MPC, // clear MPC a0151
HIT, // hit from caches a0152
SHIFT; // shift registers internal to IFU a0153
a0154
a0155
// a0156
// Combinational logic (outputs) a0157
// a0158
assign I_BUS = INSTR; // instruction a0159
assign IFU_ADDR_BUS = PC; // PC is next fetch address for IFU a0160
a0161
// Break memory access, if cache hit a0162
assign BREAK_MEM_ACC = (BTC_HIT | BTC_CORRECT | MPC_HIT) & ~NO_ACC & ~CP; a0163
a0164
// CTR in ID or BTC a0165
assign CALL_NOW = (ID_BRANCH & ID_TYPE) | (BTC_HIT & BTC_TYPE) & ~BTC_CORRECT; a0166
a0167
// Exception, if CTR in delay slot of another CTR a0168
assign EXCEPT = (ID_BRANCH | ID_CTR) & (ID_LAST_BRANCH | ID_LAST_CTR); a0169
a0170
// Delay slot in IFU a0171
assign DS_NOW = ID_BRANCH | ID_CTR; a0172
a0173
// IFU will fetch in next step a0174
assign IFU_FETCH_RQ = ~NO_FETCH & WORK_IF; a0175
a0176
// BTC corrects branch a0177
assign IFU_CORRECT = BTC_CORRECT; a0178
a0179
// a0180
// Combinational logic (internal) a0181
// a0182
assign BTC_CONFIG = CACHE_MODE[1:0]; // set BTC configuration a0183
assign MPC_CONFIG = CACHE_MODE[3:2]; // set MPC configuration a0184
assign CLR_BTC = CCLR | ~nRESET; // clear BTC a0185
assign CLR_MPC = CCLR | ~nRESET; // clear MPC a0186
assign HIT = BTC_HIT | MPC_HIT; // hit in BTC or MPC a0187
a0188
// Shift internal IFU pipeline a0189
assign SHIFT = (~NO_ACC | HIT | BTC_CORRECT | EMERG_FETCH) & WORK_IF; a0190
a0191
a0192
// a0193
// Instances a0194
// a0195
a0196
// Branch-target cache a0197
btc BTC ( a0198
BTC_DELAYSLOT, BTC_PC, BTC_HIT, BTC_CORRECT, BTC_USE_LAST, a0199
BTC_DIS_IDU, BTC_DIS_ALU, BTC_TAKEN, BTC_TYPE, a0200
INSTR, PC, JPC, LPC, FLAGS_IF, FLAGS_FD, ID_CCODE, a0201
BTC_CONFIG, ID_ANNUL, ID_BRANCH & ~EXT_BRANCH, ID_TYPE, DS_NOW, TAKEN, a0202
KU_MODE, LAST_KU_MODE, EMERG_FETCH, CLR_BTC, NEW_FLAGS, NO_ACC, a0203
WORK_IF, DO_IF, nRESET, CP a0204
); a0205
a0206
// Multi-purpose cache a0207
mpc MPC ( a0208
MPC_INSTR, MPC_HIT, a0209
ID_INSTR, PC, LPC, MPC_CONFIG, CLR_MPC, a0210
ID_BRANCH | ID_LAST_BRANCH | EXT_BRANCH, a0211
LAST_LDST, LAST_HIT, KU_MODE, LAST_KU_MODE, LAST_NO_ACC, a0212
LAST_CORRECTION, WORK_IF, DO_IF, nRESET, CP a0213
); a0214
a0215
// Branch decision logic a0216
bdl BDL (TAKEN, FLAGS_FD, ID_CCODE); a0217
a0218
// Program counter calculator a0219
pcc PCC ( a0220
PC, LPC, JPC, PC_1, PC_2, LPC_2, a0221
NEW_PC, ID_CPC, ID_DIST, ID_TYPE, SHIFT, CP a0222
); a0223
a0224
// Pipeline disable logic a0225
pdl PDL ( a0226
DIS_IDU, DIS_ALU, a0227
MPC_HIT, BTC_HIT, BTC_CORRECT, BTC_DIS_IDU, BTC_DIS_ALU, NO_ACC, a0228
ID_BRANCH & ~ID_TYPE, ID_ANNUL, TAKEN a0229
); a0230
a0231
// Instruction decode logic a0232
idl IDL ( a0233
ID_INSTR, ID_CPC, ID_DIST, ID_CCODE, a0234
ID_ANNUL, ID_BRANCH, ID_LAST_BRANCH, ID_TYPE, a0235
ID_CTR, ID_LAST_CTR, a0236
INSTR, EMERG_FETCH, SHIFT, WORK_IF, WORK_FD, nRESET, CP a0237
); a0238
a0239
// Serial mode controller a0240
smc SMC (NO_FETCH, HIT, CACHE_MODE[4], WORK_IF, nRESET, CP); a0241
a0242
// External PC logic a0243
epl EPL ( a0244
LAST_PC_BUS, LAST_USE_PCU_PC, a0245
PC_BUS, USE_PCU_PC, SHIFT, WORK_IF, nRESET, CP a0246
); a0247
a0248
// a0249
// Reset status registers a0250
// a0251
always @(negedge nRESET) begin a0252
while (~nRESET) begin a0253
NO_ACC = 1'b0; a0254
EXT_BRANCH = 1'b0; a0255
LAST_NO_ACC = 1'b0; a0256
LAST_HIT = 1'b0; a0257
LAST_CORRECTION = 1'b0; a0258
LAST_KU_MODE = 1'b0; a0259
#1; a0260
end a0261
end a0262
a0263
// a0264
// Save IFU status a0265
// a0266
// a0267
// WORK_IF is only valid at the rising clock edge; a0268
// because of this fact, it has to be saved in a register a0269
// a0270
always @(posedge CP) DO_IF = WORK_IF; a0271
a0272
// a0273
// Internal status register a0274
// a0275
// Set internal status registers with every clock a0276
// a0277
always @(posedge CP) begin a0278
if (WORK_IF) begin a0279
fork a0280
NO_ACC = #`DELTA LDST_ACC_NOW | NO_FETCH; // 1: IFU must not fetch a0281
EXT_BRANCH = #`DELTA EMERG_FETCH; // 1: external branch a0282
LAST_NO_ACC = #`DELTA NO_ACC; // 1: IFU did not fetch before a0283
LAST_HIT = #`DELTA HIT; // 1: BTC or MPC hit a0284
LAST_CORRECTION = #`DELTA BTC_CORRECT; // 1: branch was corrected a0285
LAST_KU_MODE = #`DELTA KU_MODE; // last kernel/user mode a0286
join a0287
end a0288
end a0289
a0290
// a0291
// LD/ST access pipeline a0292
// a0293
always @(posedge CP) begin a0294
if (SHIFT) begin a0295
fork a0296
LDST_ACC = #`DELTA LDST_ACC_NOW; // 1: IFU cannot fetch a0297
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