📄 3_02ifu
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//---------------------------------------------------------------------------- a0000
// a0001
// IFU: module of instruction fetch unit a0002
// a0003
// Signal encodings: a0004
// CACHE_MODE [4] = 0 : parallel mode a0005
// 1 : serial mode a0006
// CACHE_MODE [3:2] = 00 : MPC off a0007
// 01 : MPC in RIB mode a0008
// 10 : MPC in IC mode a0009
// 11 : reserved a0010
// CACHE_MODE [1:0] = 00 : BTC off a0011
// 01 : BTC stores BCCs a0012
// 10 : BTC stores CALLs a0013
// 11 : BTC stores BCCs and CALLs a0014
// a0015
//---------------------------------------------------------------------------- a0016
a0017
`define MISC_BCC_GT 4'b0110 // greater than a0018
`define MISC_BCC_LE 4'b1110 // less or equal a0019
`define MISC_BCC_GE 4'b0101 // greater or equal a0020
`define MISC_BCC_LT 4'b1101 // less than a0021
`define MISC_BCC_HI 4'b0011 // higher than a0022
`define MISC_BCC_LS 4'b1011 // lower or same a0023
`define MISC_BCC_PL 4'b0010 // plus a0024
`define MISC_BCC_MI 4'b1010 // minus a0025
`define MISC_BCC_NE 4'b0000 // not equal a0026
`define MISC_BCC_EQ 4'b1000 // equal a0027
`define MISC_BCC_VC 4'b0100 // overflow clear a0028
`define MISC_BCC_VS 4'b1100 // overflow set a0029
`define MISC_BCC_CC 4'b0001 // carry clear a0030
`define MISC_BCC_CS 4'b1001 // carry set a0031
`define MISC_BCC_T 4'b1111 // always a0032
`define MISC_BCC_F 4'b0111 // never a0033
a0034
module ifu ( a0035
I_BUS, a0036
IFU_ADDR_BUS, NPC_BUS, a0037
BREAK_MEM_ACC, CALL_NOW, DIS_IDU, DIS_ALU, EXCEPT, a0038
DS_NOW, IFU_FETCH_RQ, IFU_CORRECT, a0039
IFU_DATA_BUS, PC_BUS, CACHE_MODE, FLAGS_IF, FLAGS_FD, a0040
CP, WORK_IF, WORK_FD, CCLR, nRESET, KU_MODE, a0041
USE_PCU_PC, NEW_FLAGS, LDST_ACC_NOW, EMERG_FETCH a0042
); a0043
a0044
output [31:0] I_BUS; // instruction bus for IDU a0045
output [29:0] IFU_ADDR_BUS, // PC a0046
NPC_BUS; // last PC + 4 a0047
output BREAK_MEM_ACC, // break memory access, if cache hit a0048
CALL_NOW, // CTR a0049
DIS_IDU, // disable IDU a0050
DIS_ALU, // disable ALU a0051
EXCEPT, // branch after branch a0052
DS_NOW, // delay slot in IFU a0053
IFU_FETCH_RQ, // IFU requests fetch a0054
IFU_CORRECT; // BTC corrects a branch a0055
a0056
input [31:0] IFU_DATA_BUS; // data from BCU a0057
input [29:0] PC_BUS; // new PC a0058
input [4:0] CACHE_MODE; // cache configuration a0059
input [3:0] FLAGS_IF, // flags for BTC a0060
FLAGS_FD; // flags for BTC branch correction a0061
input CP, // system clock a0062
WORK_IF, // enable IF a0063
WORK_FD, // enable FD a0064
CCLR, // clear cache a0065
nRESET, // reset IFU a0066
KU_MODE, // kernel/user mode a0067
USE_PCU_PC, // take PC from PCU a0068
NEW_FLAGS, // flag changing instruction a0069
LDST_ACC_NOW, // MAU uses bus a0070
EMERG_FETCH; // definitely take USE_PCU_PC a0071
a0072
// Outputs a0073
wire [31:0] I_BUS; // instruction bus a0074
wire [29:0] IFU_ADDR_BUS; // PC a0075
reg [29:0] NPC_BUS; // last PC + 4 a0076
wire BREAK_MEM_ACC; // break memory access, if cache hit a0077
wire CALL_NOW; // CTR a0078
wire DIS_IDU, // disable IDU a0079
DIS_ALU; // disable ALU a0080
wire EXCEPT; // branch after branch a0081
wire DS_NOW; // delay slot in IFU a0082
wire IFU_FETCH_RQ, // IFU requests fetch a0083
IFU_CORRECT; // BTC corrects a branch a0084
a0085
// Inputs a0086
wire [31:0] IFU_DATA_BUS; // data from BCU a0087
wire [29:0] PC_BUS; // new PC a0088
wire [4:0] CACHE_MODE; // cache configuration a0089
wire [3:0] FLAGS_IF, // flags for BTC a0090
FLAGS_FD; // flags for BTC branch correction a0091
wire CP, // system clock a0092
WORK_IF, // enable IF a0093
WORK_FD, // enable FD a0094
CCLR, // clear cache a0095
nRESET, // reset IFU a0096
KU_MODE, // kernel/user mode a0097
USE_PCU_PC, // take PC from PCU a0098
NEW_FLAGS, // flag changing instruction a0099
LDST_ACC_NOW, // MAU uses bus a0100
EMERG_FETCH; // definitely take USE_PCU_PC a0101
a0102
// Local registers a0103
reg [31:0] INSTR; // output I_BUS multiplexer a0104
reg [29:0] NEW_PC; // output IFU_ADDR_BUS multiplexer a0105
reg DO_IF, // IF active a0106
NO_ACC, // IFU must not fetch a0107
EXT_BRANCH, // external branch a0108
LAST_HIT, // BTC or MPC hit a0109
LAST_CORRECTION, // branch was corrected a0110
LDST_ACC, // IFU cannot fetch a0111
LAST_LDST, // IFU could not fetch a0112
LAST_NO_ACC, // IFU did not fetch a0113
LAST_KU_MODE; // last kernel/user mode a0114
a0115
// Internal wiring a0116
wire [31:0] BTC_DELAYSLOT, // delay slot from BTC a0117
ID_INSTR, // instruction from IDL a0118
MPC_INSTR; // instruction from MPC a0119
wire [29:0] PC, // fetch address a0120
JPC, // branch address a0121
PC_1, // PC + 1 a0122
PC_2, // PC + 2 a0123
LPC, // last PC a0124
LPC_2, // last PC + 2 a0125
BTC_PC, // BTC branch target address a0126
LAST_PC_BUS, // delayed external PC a0127
ID_CPC; // CALL address from IDL a0128
wire [18:0] ID_DIST; // branch distance from IDL a0129
wire [3:0] ID_CCODE; // condition code from IDL a0130
wire [1:0] BTC_CONFIG; // configuration of BTC a0131
wire [1:0] MPC_CONFIG; // configuration of MPC a0132
wire ID_ANNUL, // ANNUL bit of IDL a0133
ID_BRANCH, // IDL has decoded branch a0134
ID_LAST_BRANCH, // IDL had decoded branch before a0135
ID_TYPE, // branch type (0:BCC, 1:CALL) from IDL a0136
ID_CTR, // IDL has decoded CTR a0137
ID_LAST_CTR, // IDL had decoded CTR before a0138
TAKEN, // branch to be taken a0139
BTC_HIT, // BTC hit a0140
BTC_CORRECT, // BTC corrects branch a0141
BTC_USE_LAST, // last fetch address when correction a0142
BTC_DIS_IDU, // BTC turns IDU off a0143
BTC_DIS_ALU, // BTC turns ALU off a0144
BTC_TAKEN, // BTC branch to be taken a0145
BTC_TYPE, // branch type of BTC (0:BCC, 1:CALL) a0146
MPC_HIT, // MPC hit a0147
NO_FETCH, // SMC requests no fetch a0148
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