3_06fru

大型risc处理器设计源代码,这是书中的代码 基于流水线的risc cpu设计

    //                                                                           e0328
    // Read write data from register                                             e0329
    //                                                                           e0330
    //------------------------------------------------------------------------   e0331
                                                                                 e0332
    always @(REG_ADDR_STORE_DATA or REGFILE[REG_ADDR_STORE_DATA] or CP)          e0333
    begin: SDL                                                                   e0334
      if (CP) begin                                                              e0335
        if (REG_ADDR_STORE_DATA != 6'b0) begin                                   e0336
          READ_STORE_DATA = REGFILE[REG_ADDR_STORE_DATA];                        e0337
        end                                                                      e0338
        else READ_STORE_DATA = 32'b0;                                            e0339
      end                                                                        e0340
    end                                                                          e0341
                                                                                 e0342
    //------------------------------------------------------------------------   e0343
    //                                                                           e0344
    // WBL (write back logic)                                                    e0345
    //                                                                           e0346
    // Write registers with data coming from WB;                                 e0347
    // data written into register file                                           e0348
    // in first half of clock are readable                                       e0349
    // in the second half, reading occurs                                        e0350
    // at the decoding of an instruction                                         e0351
    // (instruction in IDU stage).                                               e0352
    //                                                                           e0353
    //------------------------------------------------------------------------   e0354
                                                                                 e0355
    always @(REG_ADDR_C5 or DO_WB or CP or C5_BUS)                               e0356
    begin: WBL                                                                   e0357
      if (CP) begin                                                              e0358
        if ((REG_ADDR_C5 != 6'b0) && (DO_WB == `WORK)) begin                     e0359
          REGFILE[REG_ADDR_C5] = C5_BUS;                                         e0360
        end                                                                      e0361
      end                                                                        e0362
    end                                                                          e0363
                                                                                 e0364
                                                                                 e0365
    //                                                                           e0366
    // Access in second half of clock                                            e0367
    //                                                                           e0368
                                                                                 e0369
    //------------------------------------------------------------------------   e0370
    //                                                                           e0371
    // RRA (read register A)                                                     e0372
    //                                                                           e0373
    // Read register for operand A                                               e0374
    //                                                                           e0375
    //------------------------------------------------------------------------   e0376
                                                                                 e0377
    always @(REG_ADDR_A or REGFILE[REG_ADDR_A] or CP)                            e0378
    begin: RRA                                                                   e0379
      if (~CP) begin                                                             e0380
        if (REG_ADDR_A != 6'b0) READ_A = REGFILE[REG_ADDR_A];                    e0381
        else                    READ_A = 32'b0;                                  e0382
      end                                                                        e0383
    end                                                                          e0384
                                                                                 e0385
    //------------------------------------------------------------------------   e0386
    //                                                                           e0387
    // RRB (read register B)                                                     e0388
    //                                                                           e0389
    // Read register for operand B                                               e0390
    //                                                                           e0391
    //------------------------------------------------------------------------   e0392
                                                                                 e0393
    always @(REG_ADDR_B or REGFILE[REG_ADDR_B] or CP)                            e0394
    begin: RRB                                                                   e0395
      if (~CP) begin                                                             e0396
        if ( REG_ADDR_B != 6'b0) READ_B = REGFILE[REG_ADDR_B];                   e0397
        else                     READ_B = 32'b0;                                 e0398
      end                                                                        e0399
    end                                                                          e0400
                                                                                 e0401
endmodule // fru                                                                 e0402
                                                                                 e0403
                                                                                 e0404
//----------------------------------------------------------------------------   e0405
//                                                                               e0406
// FRU_EX (execution module)                                                     e0407
//                                                                               e0408
// Operating in parallel to ALU;                                                 e0409
// shifts data and register addresses in the pipeline                            e0410
//                                                                               e0411
//----------------------------------------------------------------------------   e0412
                                                                                 e0413
module fru_ex (STORE_DATA2, REG_ADDR_C, CP, WORK_ALU, STORE_DATA, REG_ADDR_C3);  e0414
  input  [31:0] STORE_DATA2;                                                     e0415
  input  [ 5:0] REG_ADDR_C;                                                      e0416
  input         CP,                                                              e0417
                WORK_ALU;                                                        e0418
  output [31:0] STORE_DATA;                                                      e0419
  output [ 5:0] REG_ADDR_C3;                                                     e0420
                                                                                 e0421
  wire   [31:0] STORE_DATA2;                                                     e0422
  wire   [ 5:0] REG_ADDR_C;                                                      e0423
  wire          CP,                                                              e0424
                WORK_ALU;                                                        e0425
  reg    [31:0] STORE_DATA;                                                      e0426
  reg    [ 5:0] REG_ADDR_C3;                                                     e0427
                                                                                 e0428
  always @(posedge CP) if (WORK_ALU) REG_ADDR_C3 = #`DELTA REG_ADDR_C;           e0429
  always @(posedge CP) if (WORK_ALU) STORE_DATA  = #`DELTA STORE_DATA2;          e0430
                                                                                 e0431
endmodule // fru_ex                                                              e0432
                                                                                 e0433
                                                                                 e0434
//----------------------------------------------------------------------------   e0435
//                                                                               e0436
// FRU_MA (memory access module)                                                 e0437
//                                                                               e0438
// Operating in parallel to MAU;                                                 e0439
// shifts register address for write-back to next pipeline stage                 e0440
//                                                                               e0441
//----------------------------------------------------------------------------   e0442
                                                                                 e0443
module fru_ma (REG_ADDR_C3, CP, WORK_MAU, REG_ADDR_C4);                          e0444
  input  [5:0] REG_ADDR_C3;                                                      e0445
  input        CP,                                                               e0446
               WORK_MAU;                                                         e0447
  output [5:0] REG_ADDR_C4;                                                      e0448
                                                                                 e0449
  wire   [5:0] REG_ADDR_C3;                                                      e0450
  wire         CP,                                                               e0451
               WORK_MAU;                                                         e0452
  reg    [5:0] REG_ADDR_C4;                                                      e0453
                                                                                 e0454
  always @(posedge CP)  if (WORK_MAU)  REG_ADDR_C4 = #`DELTA REG_ADDR_C3;        e0455
                                                                                 e0456
endmodule // fru_ma                                                              e0457
                                                                                 e0458
                                                                                 e0459
//----------------------------------------------------------------------------   e0460
//                                                                               e0461
// FRU_WB (write back module)                                                    e0462
//                                                                               e0463
// Module declaration for write-back unit (WB);                                  e0464
// stores write-back address REG_ADDR_C5 and C_BUS                               e0465
//                                                                               e0466
//----------------------------------------------------------------------------   e0467
                                                                                 e0468
module fru_wb (C4_BUS, REG_ADDR_C4, WORK_WB, CP, C5_BUS, REG_ADDR_C5);           e0469
  input  [31:0] C4_BUS;                                                          e0470
  input  [ 5:0] REG_ADDR_C4;                                                     e0471
  input         WORK_WB,                                                         e0472
                CP;                                                              e0473
  output [31:0] C5_BUS;                                                          e0474
  output [ 5:0] REG_ADDR_C5;                                                     e0475
                                                                                 e0476
  wire   [31:0] C4_BUS;                                                          e0477
  wire   [ 5:0] REG_ADDR_C4;                                                     e0478
  wire          WORK_WB,                                                         e0479
                CP;                                                              e0480
  reg    [31:0] C5_BUS;                                                          e0481
  reg    [ 5:0] REG_ADDR_C5;                                                     e0482
                                                                                 e0483
  always @(posedge CP)  if (WORK_WB)  REG_ADDR_C5 = #`DELTA REG_ADDR_C4;         e0484
  always @(posedge CP)  if (WORK_WB)  C5_BUS      = #`DELTA C4_BUS;              e0485
                                                                                 e0486
endmodule // fru_wb                                                              e0487