📄 3_06fru
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7'b01111??: // internal interrupt, upper registers e0164
REG_ADDR_C = {4'b1000,ADDR_C[1:0]}; e0165
7'b1?111??: // hardware interrupt, upper registers e0166
REG_ADDR_C = {4'b1001,ADDR_C[1:0]}; e0167
default: // lower registers e0168
REG_ADDR_C = {1'b0,ADDR_C}; e0169
endcase e0170
e0171
// e0172
// Register address transformation ADDR_A -> REG_ADDR_A e0173
// e0174
casez ({INT_STATE,ADDR_A}) e0175
7'b01111??: // internal interrupt, upper registers e0176
REG_ADDR_A = {4'b1000,ADDR_A[1:0]}; e0177
7'b1?111??: // hardware interrupt, upper registers e0178
REG_ADDR_A = {4'b1001,ADDR_A[1:0]}; e0179
default: // lower registers e0180
REG_ADDR_A = {1'b0,ADDR_A}; e0181
endcase e0182
e0183
// e0184
// Register address transformation ADDR_B -> REG_ADDR_B e0185
// e0186
casez ({INT_STATE,ADDR_B}) e0187
7'b01111??: // internal interrupt, upper registers e0188
REG_ADDR_B = {4'b1000,ADDR_B[1:0]}; e0189
7'b1?111??: // hardware interrupt, upper registers e0190
REG_ADDR_B = {4'b1001,ADDR_B[1:0]}; e0191
default: // lower registers e0192
REG_ADDR_B = {1'b0,ADDR_B}; e0193
endcase e0194
end e0195
e0196
//-------------------------------------------------------------------------- e0197
// e0198
// CMP (forwarding comparator) e0199
// e0200
// The transformed register address is e0201
// compared with the corresponding address e0202
// presently in some pipeline stage. e0203
// When coinciding, output multiplexer SEL_X is switched e0204
// to the corresponding stage. Earlier pipeline stages e0205
// are prefered. Only pipeline stages with valid e0206
// work signal are considered for a forwarding. e0207
// Register 0 is not forwarded. e0208
// e0209
//-------------------------------------------------------------------------- e0210
e0211
always @(REG_ADDR_A or REG_ADDR_B or REG_ADDR_STORE_DATA or e0212
REG_ADDR_C3 or REG_ADDR_C4 or REG_ADDR_C5 or e0213
USE_IMMEDIATE or USE_SREG_DATA or INT_STATE or e0214
DO_ALU or DO_MAU or DO_WB ) e0215
begin: CMP e0216
e0217
// e0218
// ALU operand A e0219
// e0220
if ((REG_ADDR_A==REG_ADDR_C3) && (DO_ALU==`WORK) && (|REG_ADDR_A)) e0221
SEL_A = `TAKE2_C3; e0222
else begin e0223
if ((REG_ADDR_A==REG_ADDR_C4) && (DO_MAU==`WORK) && (|REG_ADDR_A)) e0224
SEL_A = `TAKE2_C4; e0225
else SEL_A = `TAKE2_ADDR; e0226
end e0227
e0228
// e0229
// ALU operand B e0230
// e0231
// An immediate has priority, then a special e0232
// register, then the pipeline stages e0233
// e0234
if (USE_IMMEDIATE) e0235
SEL_B = `TAKE3_IMM; e0236
else begin e0237
if (USE_SREG_DATA) e0238
SEL_B = `TAKE3_SREG; e0239
else begin e0240
if ((REG_ADDR_B==REG_ADDR_C3) && (DO_ALU==`WORK) && (|REG_ADDR_B)) e0241
SEL_B = `TAKE3_C3; e0242
else begin e0243
if ((REG_ADDR_B==REG_ADDR_C4) && (DO_MAU==`WORK) && (|REG_ADDR_B)) e0244
SEL_B = `TAKE3_C4; e0245
else SEL_B = `TAKE3_ADDR; e0246
end e0247
end e0248
end e0249
e0250
// e0251
// Store data e0252
// e0253
if ((REG_ADDR_STORE_DATA==REG_ADDR_C3) && (DO_ALU==`WORK) e0254
&& (|REG_ADDR_STORE_DATA)) e0255
SEL_S = `TAKE2_C3; e0256
else begin e0257
if ((REG_ADDR_STORE_DATA==REG_ADDR_C4) && (DO_MAU==`WORK) e0258
&& (|REG_ADDR_STORE_DATA)) e0259
SEL_S = `TAKE2_C4; e0260
else SEL_S = `TAKE2_ADDR; e0261
end e0262
end e0263
e0264
//-------------------------------------------------------------------------- e0265
// e0266
// FSL (forwarding selection logic) e0267
// e0268
// This multiplexer puts correct values to A_BUS, B_BUS, e0269
// and STORE_DATA depending on the forwarding logic. e0270
// e0271
//-------------------------------------------------------------------------- e0272
e0273
always @(SEL_A or SEL_B or SEL_S or READ_A or READ_B or READ_STORE_DATA or e0274
C3_BUS or C4_BUS or IMMEDIATE or SREG_DATA) e0275
begin: FSL e0276
e0277
// e0278
// ALU operand A (MUX_A) e0279
// e0280
case(SEL_A) e0281
`TAKE2_ADDR: A_BUS = READ_A; e0282
`TAKE2_C3: A_BUS = C3_BUS; e0283
`TAKE2_C4: A_BUS = C4_BUS; e0284
endcase e0285
e0286
// e0287
// ALU operand B (MUX_B) e0288
// e0289
case (SEL_B) e0290
`TAKE3_ADDR: B_BUS = READ_B; e0291
`TAKE3_C3: B_BUS = C3_BUS; e0292
`TAKE3_C4: B_BUS = C4_BUS; e0293
`TAKE3_IMM: B_BUS = IMMEDIATE; e0294
`TAKE3_SREG: B_BUS = SREG_DATA; e0295
endcase e0296
e0297
// e0298
// Store data (MUX_S) e0299
// e0300
case (SEL_S) e0301
`TAKE2_ADDR: STORE_DATA2 = READ_STORE_DATA; e0302
`TAKE2_C3: STORE_DATA2 = C3_BUS; e0303
`TAKE2_C4: STORE_DATA2 = C4_BUS; e0304
endcase e0305
end e0306
e0307
//-------------------------------------------------------------------------- e0308
// e0309
// RAL (register access logic) e0310
// e0311
// Only registers different from register 0 are e0312
// accessed. A partition in first and second e0313
// half of the clock was chosen considering a e0314
// future realization with a two-port RAM. e0315
// Precise timing is required, as this is e0316
// not the normal register transfer logic. e0317
// e0318
//-------------------------------------------------------------------------- e0319
e0320
// e0321
// Access during first half of clock e0322
// e0323
e0324
//------------------------------------------------------------------------ e0325
// e0326
// SDL (store data logic) e0327
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