📄 3_06fru
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//---------------------------------------------------------------------------- e0000
// e0001
// FRU: module of forwarding and register unit e0002
// e0003
// Structure: e0004
// register file declaration e0005
// address converter of register addresses depending on interrupt status e0006
// comparator for forwarding e0007
// bus switch put proper values to buses, forwarding e0008
// register accesses ordered by clock phases e0009
// e0010
// The following submodules contain things belonging e0011
// logically to other pipeline stages: e0012
// FRU_EX works in parallel to the ALU e0013
// FRU_MA works in parallel to the MAU e0014
// FRU_WB constitutes the write-back stage of the pipeline e0015
// e0016
// The FRU provides operands for ALU and MAU and contains e0017
// the write-back stage as the last pipeline stage, e0018
// which writes values back to the register file. e0019
// Values are fetched from the immediate bus or the special register bus e0020
// or from the general-purpose registers also contained in the module. e0021
// If register values still in the pipeline are required, e0022
// they are made available by forwarding before e0023
// arriving in the registers. e0024
// e0025
// Connections: e0026
// mainly with IDU, to which the main module of FRU belongs e0027
// w.r.t. time, but also to ALU, MAU, and PCU (work signals); e0028
// except for work signals, everything is taken e0029
// asynchronously and transfered synchronously. e0030
// e0031
// Structure: e0032
// The main module contains basically logic. e0033
// As states, there are some work signals taken e0034
// synchronously and held, and there is the register file. e0035
// Moreover, there are some states in submodules, e0036
// in which data are transfered synchronously. e0037
// e0038
//---------------------------------------------------------------------------- e0039
e0040
// Definitions for MUX signals SEL_A and SEL_B e0041
`define WORK 1'b1 e0042
`define TAKE2_ADDR 2'b00 e0043
`define TAKE2_C3 2'b01 e0044
`define TAKE2_C4 2'b10 e0045
`define TAKE3_ADDR 3'b000 e0046
`define TAKE3_C3 3'b001 e0047
`define TAKE3_C4 3'b010 e0048
`define TAKE3_IMM 3'b100 e0049
`define TAKE3_SREG 3'b101 e0050
e0051
module fru ( e0052
A_BUS, B_BUS, STORE_DATA, e0053
SREG_DATA, IMMEDIATE, C3_BUS, C4_BUS, e0054
ADDR_A, ADDR_B, ADDR_C, ADDR_STORE_DATA, e0055
INT_STATE, USE_IMMEDIATE, e0056
CP, STEP, WORK_ALU, e0057
WORK_MAU, WORK_WB, USE_SREG_DATA e0058
); e0059
e0060
e0061
// Outputs e0062
output [31:0] A_BUS, // data bus A e0063
B_BUS, // data bus B e0064
STORE_DATA; // delayed write data for MAU e0065
e0066
// Inputs e0067
input [31:0] SREG_DATA, // data from special register e0068
IMMEDIATE, // immediate for data bus B e0069
C3_BUS, // result bus C3 for forwarding e0070
C4_BUS; // result bus C4 for forwarding and WB e0071
input [4:0] ADDR_A, // register address for data bus A e0072
ADDR_B, // register address for data bus B e0073
ADDR_C, // register address for result bus C e0074
ADDR_STORE_DATA; // register address for store data e0075
input [1:0] INT_STATE; // selection of interrupt overlay register set e0076
input USE_IMMEDIATE, // immediate bus valid e0077
CP, // system clock e0078
STEP, // BCU has finished operation e0079
WORK_ALU, // ALU active e0080
WORK_MAU, // MAU active e0081
WORK_WB, // WB active e0082
USE_SREG_DATA; // use data from special register e0083
e0084
// Declarations e0085
reg [31:0] REGFILE[0:39]; // processor register file e0086
reg [31:0] A_BUS, // data bus A e0087
B_BUS; // data bus B e0088
wire [31:0] STORE_DATA; // delayed write data for MAU e0089
reg [31:0] STORE_DATA2, // write data for MAU: register -> EX e0090
READ_STORE_DATA, // data from register ADDR_STORE_DATA e0091
READ_A, // data from register ADDR_A e0092
READ_B; // data from register ADDR_B e0093
wire [31:0] C5_BUS; // result data from MAU: WB -> FRU e0094
reg [5:0] REG_ADDR_C, // register address according to INT_STATE e0095
REG_ADDR_A, // register address according to INT_STATE e0096
REG_ADDR_B, // register address according to INT_STATE e0097
REG_ADDR_STORE_DATA; // register address according to INT_STATE e0098
wire [5:0] REG_ADDR_C3, // register address for result: EX -> MA e0099
REG_ADDR_C4, // register address for result: MA -> WB e0100
REG_ADDR_C5; // register address for result: WB -> FRU e0101
reg [1:0] SEL_A, // selection for A_BUS e0102
SEL_S; // selection for STORE_DATA e0103
reg [2:0] SEL_B; // selection for B_BUS e0104
reg DO_ALU, // ALU was activated e0105
DO_MAU, // MAU was activated e0106
DO_WB; // WB was activated e0107
e0108
// e0109
// Instances e0110
// e0111
e0112
fru_ex FRU_EX ( e0113
STORE_DATA2, REG_ADDR_C, CP, WORK_ALU, STORE_DATA, REG_ADDR_C3 e0114
); e0115
e0116
fru_ma FRU_MA (REG_ADDR_C3, CP, WORK_MAU, REG_ADDR_C4); e0117
e0118
fru_wb FRU_WB (C4_BUS, REG_ADDR_C4, WORK_WB, CP, C5_BUS, REG_ADDR_C5); e0119
e0120
e0121
// e0122
// Take inputs synchronously e0123
// e0124
always @(posedge CP) if (STEP) DO_ALU = #`DELTA WORK_ALU; e0125
always @(posedge CP) if (STEP) DO_MAU = #`DELTA WORK_MAU; e0126
always @(posedge CP) if (STEP) DO_WB = #`DELTA WORK_WB; e0127
e0128
//-------------------------------------------------------------------------- e0129
// e0130
// RAC (register address converter) e0131
// e0132
// Register addresses are transformed depending on the e0133
// interrupt status. Two comparators and some wiring e0134
// suffice to generate the address for the register e0135
// file. This is necessary, as for every interrupt e0136
// status, the upper four registers are private e0137
// and to be superimposed correspondingly. e0138
// The generated addresses are REG_XXX and are e0139
// further used by the forwarding comparators e0140
// and for register accesses. e0141
// These addresses are shifted in the pipeline. e0142
// e0143
//-------------------------------------------------------------------------- e0144
e0145
always @(ADDR_A or ADDR_B or ADDR_C or ADDR_STORE_DATA or INT_STATE) e0146
begin: RAC e0147
// e0148
// Register address transformation ADDR_STORE_DATA -> REG_ADDR_STORE_DATA e0149
// e0150
casez ({INT_STATE,ADDR_STORE_DATA}) e0151
7'b01111??: // internal interrupt, upper registers e0152
REG_ADDR_STORE_DATA = {4'b1000,ADDR_STORE_DATA[1:0]}; e0153
7'b1?111??: // hardware interrupt, upper registers e0154
REG_ADDR_STORE_DATA = {4'b1001,ADDR_STORE_DATA[1:0]}; e0155
default: // lower registers e0156
REG_ADDR_STORE_DATA = {1'b0,ADDR_STORE_DATA}; e0157
endcase e0158
e0159
// e0160
// Register address transformation ADDR_C -> REG_ADDR_C e0161
// e0162
casez ({INT_STATE,ADDR_C}) e0163
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