📄 4_1vos
字号:
// c0000400
// c0000400 ; determine Operand2 and load into R29
// c0000400 ; decide if Op2 is a register or an immediate
52068008 // c0000400 LSL.f R00, R26, 8 ; register?
FCC8000B // c0000404 Bcs.a UnImp_Rs2 ; if so, continue elsewhere and clear
50CE801B // c0000408 LSL R25, R26, 27 ; bits by register no. (Rs2)
// c000040c ;
// c000040c ; store Op2 (Imm) in R29
61E80000 // c000040c CLR R29 ; store
52068013 // c0000410 LSL.f R00, R26, 19 ; is immediate negative?
FCC80002 // c0000414 Bcs.a UnImp_Imm ; if so,
E0EFFFFF // c0000418 LDH R29, -1 ; preset register
50CE8012 // c000041c UnImp_Imm: LSL R25, R26, 18 ; clear upper bits(Op-Rd-Rs1)
54CE4012 // c0000420 LSR R25, R25, 18 ; and combine immediate in R29
45EF4019 // c0000424 OR R29, R29, R25 ; with sign
FC780048 // c0000428 Bt UnImp_Rs1 ; continue
50CE800D // c000042c LSL R25, R26, 13 ; with Op1
// c0000430 ;
// c0000430 ; store Op2 (Rs2) in R29
// c0000430 ;DelaySlot LSL R25, R26, 27 ; clear bits by REG no. (Rs2)
54CE4018 // c0000430 UnImp_Rs2: LSR R25, R25, 24 ; compute (REG no. from Op2)*8
E0DE0000 // c0000434 LDH R27, UnImp_Rs2Tb ; and add to
44DEC448 // c0000438 OR R27, R27, UnImp_Rs2Tb & $1FFF ; branch table
61DEC019 // c000043c ADD R27, R27, R25 ; as distance
EB00001B // c0000440 JMP R27 ; compute and continue
50CE800D // c0000444 LSL R25, R26, 13 ; with Op1
// c0000448 ;------------------------------------------------------------------
// c0000448 ; branch table
FC780040 // c0000448 UnImp_Rs2Tb:Bt UnImp_Rs1 ; continue with Op1
61E80000 // c000044c MOV R29, R00 ; load Op2 to R29
// c0000450 ;
FC78003E // c0000450 Bt UnImp_Rs1 ; continue with Op1
61E80001 // c0000454 MOV R29, R01 ; load Op2 to R29
// c0000458 ;
FC78003C // c0000458 Bt UnImp_Rs1 ; continue with Op1
61E80002 // c000045c MOV R29, R02 ; load Op2 to R29
// c0000460 ;
FC78003A // c0000460 Bt UnImp_Rs1 ; continue with Op1
61E80003 // c0000464 MOV R29, R03 ; load Op2 to R29
// c0000468 ;
FC780038 // c0000468 Bt UnImp_Rs1 ; continue with Op1
61E80004 // c000046c MOV R29, R04 ; load Op2 to R29
// c0000470 ;
FC780036 // c0000470 Bt UnImp_Rs1 ; continue with Op1
61E80005 // c0000474 MOV R29, R05 ; load Op2 to R29
// c0000478 ;
FC780034 // c0000478 Bt UnImp_Rs1 ; continue with Op1
61E80006 // c000047c MOV R29, R06 ; load Op2 to R29
// c0000480 ;
FC780032 // c0000480 Bt UnImp_Rs1 ; continue with Op1
61E80007 // c0000484 MOV R29, R07 ; load Op2 to R29
// c0000488 ;
FC780030 // c0000488 Bt UnImp_Rs1 ; continue with Op1
61E80008 // c000048c MOV R29, R08 ; load Op2 to R29
// c0000490 ;
FC78002E // c0000490 Bt UnImp_Rs1 ; continue with Op1
61E80009 // c0000494 MOV R29, R09 ; load Op2 to R29
// c0000498 ;
FC78002C // c0000498 Bt UnImp_Rs1 ; continue with Op1
61E8000A // c000049c MOV R29, R10 ; load Op2 to R29
// c00004a0 ;
FC78002A // c00004a0 Bt UnImp_Rs1 ; continue with Op1
61E8000B // c00004a4 MOV R29, R11 ; load Op2 to R29
// c00004a8 ;
FC780028 // c00004a8 Bt UnImp_Rs1 ; continue with Op1
61E8000C // c00004ac MOV R29, R12 ; load Op2 to R29
// c00004b0 ;
FC780026 // c00004b0 Bt UnImp_Rs1 ; continue with Op1
61E8000D // c00004b4 MOV R29, R13 ; load Op2 to R29
// c00004b8 ;
FC780024 // c00004b8 Bt UnImp_Rs1 ; continue with Op1
61E8000E // c00004bc MOV R29, R14 ; load Op2 to R29
// c00004c0 ;
FC780022 // c00004c0 Bt UnImp_Rs1 ; continue with Op1
61E8000F // c00004c4 MOV R29, R15 ; load Op2 to R29
// c00004c8 ;
FC780020 // c00004c8 Bt UnImp_Rs1 ; continue with Op1
61E80010 // c00004cc MOV R29, R16 ; load Op2 to R29
// c00004d0 ;
FC78001E // c00004d0 Bt UnImp_Rs1 ; continue with Op1
61E80011 // c00004d4 MOV R29, R17 ; load Op2 to R29
// c00004d8 ;
FC78001C // c00004d8 Bt UnImp_Rs1 ; continue with Op1
61E80012 // c00004dc MOV R29, R18 ; load Op2 to R29
// c00004e0 ;
FC78001A // c00004e0 Bt UnImp_Rs1 ; continue with Op1
61E80013 // c00004e4 MOV R29, R19 ; load Op2 to R29
// c00004e8 ;
FC780018 // c00004e8 Bt UnImp_Rs1 ; continue with Op1
61E80014 // c00004ec MOV R29, R20 ; load Op2 to R29
// c00004f0 ;
FC780016 // c00004f0 Bt UnImp_Rs1 ; continue with Op1
61E80015 // c00004f4 MOV R29, R21 ; load Op2 to R29
// c00004f8 ;
FC780014 // c00004f8 Bt UnImp_Rs1 ; continue with Op1
61E80016 // c00004fc MOV R29, R22 ; load Op2 to R29
// c0000500 ;
FC780012 // c0000500 Bt UnImp_Rs1 ; continue with Op1
61E80017 // c0000504 MOV R29, R23 ; load Op2 to R29
// c0000508 ;
FC780010 // c0000508 Bt UnImp_Rs1 ; continue with Op1
0EEE0018 // c000050c LD.q R29, R24, 24*4 ; load Op2 to R29
// c0000510 ;
FC78000E // c0000510 Bt UnImp_Rs1 ; continue with Op1
0EEE0019 // c0000514 LD.q R29, R24, 25*4 ; load Op2 to R29
// c0000518 ;
FC78000C // c0000518 Bt UnImp_Rs1 ; continue with Op1
0EEE001A // c000051c LD.q R29, R24, 26*4 ; load Op2 to R29
// c0000520 ;
FC78000A // c0000520 Bt UnImp_Rs1 ; continue with Op1
0EEE001B // c0000524 LD.q R29, R24, 27*4 ; load Op2 to R29
// c0000528 ;
FC780008 // c0000528 Bt UnImp_Rs1 ; continue with Op1
0EEE001C // c000052c LD.q R29, R24, 28*4 ; load Op2 to R29
// c0000530 ;
FC780006 // c0000530 Bt UnImp_Rs1 ; continue with Op1
0EEE001D // c0000534 LD.q R29, R24, 29*4 ; load Op2 to R29
// c0000538 ;
FC780004 // c0000538 Bt UnImp_Rs1 ; continue with Op1
0EEE001E // c000053c LD.q R29, R24, 30*4 ; load Op2 to R29
// c0000540 ;
FC780002 // c0000540 Bt UnImp_Rs1 ; continue with Op1
0EEE001F // c0000544 LD.q R29, R24, 31*4 ; load Op2 to R29
// c0000548 ;------------------------------------------------------------------
// c0000548
// c0000548 ; compute Operand1 and load into R27
// c0000548 ;DelaySlot LSL R25, R26, 13 ; compute (REG no from Op1)*8
54CE4018 // c0000548 UnImp_Rs1: LSR R25, R25, 24 ; and add to
E0DE0000 // c000054c LDH R27, UnImp_Rs1Tb ; branch table
44DEC560 // c0000550 OR R27, R27, UnImp_Rs1Tb & $1FFF ; as
61DEC019 // c0000554 ADD R27, R27, R25 ; distance
EB00001B // c0000558 JMP R27 ; continue
54CE801A // c000055c LSR R25, R26, 26 ;
// c0000560 ;------------------------------------------------------------------
// c0000560 ; branch table
FC780040 // c0000560 UnImp_Rs1Tb:Bt UnImp_OpCd ; continue with opcode analysis
61D80000 // c0000564 MOV R27, R00 ; load Op1 to R27
// c0000568 ;
FC78003E // c0000568 Bt UnImp_OpCd ; continue with opcode analysis
61D80001 // c000056c MOV R27, R01 ; load Op1 to R27
// c0000570 ;
FC78003C // c0000570 Bt UnImp_OpCd ; continue with opcode analysis
61D80002 // c0000574 MOV R27, R02 ; load Op1 to R27
// c0000578 ;
FC78003A // c0000578 Bt UnImp_OpCd ; continue with opcode analysis
61D80003 // c000057c MOV R27, R03 ; load Op1 to R27
// c0000580 ;
FC780038 // c0000580 Bt UnImp_OpCd ; continue with opcode analysis
61D80004 // c0000584 MOV R27, R04 ; load Op1 to R27
// c0000588 ;
FC780036 // c0000588 Bt UnImp_OpCd ; continue with opcode analysis
61D80005 // c000058c MOV R27, R05 ; load Op1 to R27
// c0000590 ;
FC780034 // c0000590 Bt UnImp_OpCd ; continue with opcode analysis
61D80006 // c0000594 MOV R27, R06 ; load Op1 to R27
// c0000598 ;
FC780032 // c0000598 Bt UnImp_OpCd ; continue with opcode analysis
61D80007 // c000059c MOV R27, R07 ; load Op1 to R27
// c00005a0 ;
FC780030 // c00005a0 Bt UnImp_OpCd ; continue with opcode analysis
61D80008 // c00005a4 MOV R27, R08 ; load Op1 to R27
// c00005a8 ;
FC78002E // c00005a8 Bt UnImp_OpCd ; continue with opcode analysis
61D80009 // c00005ac MOV R27, R09 ; load Op1 to R27
// c00005b0 ;
FC78002C // c00005b0 Bt UnImp_OpCd ; continue with opcode analysis
61D8000A // c00005b4 MOV R27, R10 ; load Op1 to R27
// c00005b8 ;
FC78002A // c00005b8 Bt UnImp_OpCd ; continue with opcode analysis
61D8000B // c00005bc MOV R27, R11 ; load Op1 to R27
// c00005c0 ;
FC780028 // c00005c0 Bt UnImp_OpCd ; continue with opcode analysis
61D8000C // c00005c4 MOV R27, R12 ; load Op1 to R27
// c00005c8 ;
FC780026 // c00005c8 Bt UnImp_OpCd ; continue with opcode analysis
61D8000D // c00005cc MOV R27, R13 ; load Op1 to R27
// c00005d0 ;
FC780024 // c00005d0 Bt UnImp_OpCd ; continue with opcode analysis
61D8000E // c00005d4 MOV R27, R14 ; load Op1 to R27
// c00005d8 ;
FC780022 // c00005d8 Bt UnImp_OpCd ; continue with opcode analysis
61D8000F // c00005dc MOV R27, R15 ; load Op1 to R27
// c00005e0 ;
FC780020 // c00005e0 Bt UnImp_OpCd ; continue with opcode analysis
61D80010 // c00005e4 MOV R27, R16 ; load Op1 to R27
// c00005e8 ;
FC78001E // c00005e8 Bt UnImp_OpCd ; continue with opcode analysis
61D80011 // c00005ec MOV R27, R17 ; load Op1 to R27
// c00005f0 ;
FC78001C // c00005f0 Bt UnImp_OpCd ; continue with opcode analysis
61D80012 // c00005f4 MOV R27, R18 ; load Op1 to R27
// c00005f8 ;
FC78001A // c00005f8 Bt UnImp_OpCd ; continue with opcode analysis
61D80013 // c00005fc MOV R27, R19 ; load Op1 to R27
// c0000600 ;
FC780018 // c0000600 Bt UnImp_OpCd ; continue with opcode analysis
61D80014 // c0000604 MOV R27, R20 ; load Op1 to R27
// c0000608 ;
FC780016 // c0000608 Bt UnImp_OpCd ; continue with opcode analysis
61D80015 // c000060c MOV R27, R21 ; load Op1 to R27
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -