📄 4_1vos
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60E00074 // c00002ec MOV R28, 29*4 ; store INT-ID (*4)
// c00002f0
// c00002f0 ; INT # 30, SWI # 14
FC780004 // c00002f0 Bt NotSpIntSrv ; INT not supported by OS
60E00078 // c00002f4 MOV R28, 30*4 ; store INT-ID (*4)
// c00002f8
// c00002f8 ; INT # 31, SWI # 15
FC78002B // c00002f8 Bt SWI15Srv ; branch to info request server
6B004000 // c00002fc TST.f R01 ; test contents of R01
// c0000300
// c0000300
// c0000300
// c0000300
// c0000300
// c0000300 ;##############################################################################
// c0000300 ; Interrupt routines
// c0000300 ; ==================
// c0000300
// c0000300
// c0000300
// c0000300 ; "Interrupt not supported"
// c0000300 ; -------------------------
// c0000300 ; Test if interrupt is supported by the additional interrupt server and branch
// c0000300 ; to service routine or stop system.
// c0000300 ; This section is for test purposes and supports the individual extension
// c0000300 ; of the vector by test programs.
// c0000300 ;OS-Vek Bt NotSpIntSrv ; INT not supported by OS
// c0000300 ;OS-Vek MOV R28, <INT# * 4> ; store INT-ID (*4)
E0EA0000 // c0000300 NotSpIntSrv:LDH R29, AddIntSrv ; address of additional interrupt server
44EF4000 // c0000304 OR R29, R29, AddIntSrv & $1FFF ; load vector
0FF7401C // c0000308 LD R30, R29, R28 ; load entry of interrupt
0EFF4020 // c000030c LD R31, R29, 32*4 ; and "last chance"
6A07BFFB // c0000310 CMP.f R30, -4-1 ;
FC980004 // c0000314 Bhi.a NotSpInt_L2 ; if there is no service routine,
6A07FFFB // c0000318 CMP.f R31, -4-1 ; check "last chance";
EB00001E // c000031c NotSpInt_L1:JMP R30 ; else branch to service routine
49000000 // c0000320 NOP ;
// c0000324 ;
FC5FFFFE // c0000324 NotSpInt_L2:Bls NotSpInt_L1 ; does service routine for
// c0000324 ; "last chance" exist?
61F0001F // c0000328 MOV R30, R31 ; load branch target
FF000000 // c000032c HALT ; otherwise HALT
// c0000330
// c0000330
// c0000330
// c0000330 ; Page fault interrupt server HWI#01/INT#01
// c0000330 ; ---------------------------
// c0000330 ; The page fault address is transferred to the hardware page daemon (HWPD).
// c0000330 ;OS-Vek Bt PgFltISrv ; branch to page fault interrupt server
// c0000330 ;OS-Vek LRFS R28, HIADR ; load page fault address
E0EC0000 // c0000330 PgFltISrv: LDH R29, HWPD ; load High-Adr
44EF4000 // c0000334 OR R29, R29, HWPD & $1FFF ; load Low-Adr
2EE74000 // c0000338 ST.q R28, R29, 0 ; enable fault page for USER
FE000000 // c000033c RETI ;
E7000000 // c0000340 CLC ;
// c0000344
// c0000344
// c0000344
// c0000344 ; TIMER interrupt server
// c0000344 ; ---------------------- SWI#01/INT#16
// c0000344 ; A control word is transferred to the timer in register R01. Its 16 bits
// c0000344 ; are divided as follows:
// c0000344 ; R01[14..0]: number of quarter cycles until timer interrupt
// c0000344 ; R01[15]: periodic (1) or once (0)
// c0000344 ;OS-Vek Bt SWI01Srv ; branch to SWI01 int server
// c0000344 ;OS-Vek LDH R28, TIMER ; load High-Adr
44E70004 // c0000344 SWI01Srv: OR R28, R28, TIMER & $1FFF ; load Low-Adr
FE000000 // c0000348 RETI ; transfer control word and
2E0F0000 // c000034c ST.q R01, R28, 0 ; return
// c0000350
// c0000350
// c0000350
// c0000350 ; (Optional) timer event server HWI#03/INT#03
// c0000350 ; -----------------------------
// c0000350 ; For many tests, only the interrupt itself and not its reaction are of
// c0000350 ; interest. For this, there is a minimal service routine.
FE000000 // c0000350 TimerEvSrv: RETI ; return
49000000 // c0000354 NOP ;
// c0000358
// c0000358
// c0000358
// c0000358 ; New interrupt vector SWI#02/INT#17
// c0000358 ; --------------------
// c0000358 ; Depending on the INT-ID in register R0 it is tested if a service routine
// c0000358 ; was assigned to the interrupt. If no such routine exists so far, the value
// c0000358 ; in R02 is aligned and taken as the start address of the new service routine.
// c0000358 ; When calling this routine, it has to be R02 <> -1.
// c0000358 ; A successful entry is indicated by
// c0000358 ; R01 = INT-ID & R02 old entry.
// c0000358 ; R02 = -2 | -4 indicates that the entry was not taken.
// c0000358 ; An unsuccessful entry is indicated by
// c0000358 ; R01 > 16 (unsigned) if INT-ID was invalid
// c0000358 ; R01 = -1 if INT is permanently occupied by OS.
// c0000358 ;OS-Vek Bt SWI02Srv ; branch to SWI02 int server
// c0000358 ;OS-Vek LDH R28, AddIntSrv ; address of additional interrupt server
44E70000 // c0000358 SWI02Srv: OR R28, R28, AddIntSrv & $1FFF ; load vector
6A004020 // c000035c CMP.f R01, 32 ; INT-ID correct?
FC180008 // c0000360 Bhi SWI02Srv_L1 ;
// c0000364 ;
50E84002 // c0000364 LSL R29, R01, 2 ; determine old service address
0FF7001D // c0000368 LD R30, R28, R29 ; and load
40F8BFFC // c000036c AND R31, R02, -4 ; align service address
6A07BFFF // c0000370 CMP.f R30, -1 ; test old address/entry
FC800003 // c0000374 Bne.a SWI02Srv_L1 ; if not occupied by OS,
2FFF001D // c0000378 ST R31, R28, R29 ; store new address
// c000037c ;
60083FFF // c000037c MOV R01, -1 ; and mark
// c0000380 ;
FE000000 // c0000380 SWI02Srv_L1:RETI ; return
6110001E // c0000384 MOV R02, R30 ; transfer old entry
// c0000388
// c0000388
// c0000388
// c0000388 ; Kernel mode request interrupt server SWI#03/INT#18
// c0000388 ; ------------------------------------
// c0000388 ; The present program is set to kernel mode
// c0000388 ;OS-Vek Bt SWI03Srv ; branch to SWI03 int server
// c0000388 ;OS-Vek LRFS R28, SISR ;
44E70080 // c0000388 SWI03Srv: OR R28, R28, $80 ; set kernel bit in
EB40001C // c000038c SRIS SISR, R28 ; User (/SWI) SR
FE000000 // c0000390 RETI ; return
49000000 // c0000394 NOP ;
// c0000398
// c0000398
// c0000398
// c0000398 ; ClockTime request interrupt server SWI#04/INT#19
// c0000398 ; ----------------------------------
// c0000398 ; Transfer system clock to R01
// c0000398 ;OS-Vek Bt SWI04Srv ; branch to SWI04 int server
// c0000398 ;OS-Vek LDH R28, CLKTM ; address of CLKTM component
0E0F0002 // c0000398 SWI04Srv: LD R01, R28, CLKTM & $1FFF ; load system time
FE000000 // c000039c RETI ; return
E7000000 // c00003a0 CLC ; ensure no cache hits
// c00003a4
// c00003a4
// c00003a4
// c00003a4 ; Info request server SWI#15/INT#31
// c00003a4 ; -------------------
// c00003a4 ; The required information is transferred depending on register R01.
// c00003a4 ; If R01=0, the OS version is transferred in R01.
// c00003a4 ;OS-Vek Bt SWI15Srv ; branch to Info request server
// c00003a4 ;OS-Vek TST.f R01, 0 ; test R01
FC000004 // c00003a4 SWI15Srv: Bne SWI15_Exit ; exit
49000000 // c00003a8 NOP ;
E00A1298 // c00003ac LDH R01, OS_Vers ; OS version
44084022 // c00003b0 OR R01, R01, OS_Vers & $1FFF; load
FE000000 // c00003b4 SWI15_Exit: RETI ; and
49000000 // c00003b8 NOP ; return
// c00003bc
// c00003bc
// c00003bc
// c00003bc ;------------------------------------------------------------------------------
// c00003bc ;
// c00003bc ; Unimplemented instruction interrupt server EXC#03/INT#11
// c00003bc ;
// c00003bc ; Emulate unimplemented instructions having a reserved OpCode.
// c00003bc ; These are
// c00003bc ; MUL(.f) with OpCode 011110**
// c00003bc ; DIV(.f) with OpCode 011111**
// c00003bc ;
// c00003bc ; Attention: problem for Min-Int, as not invertable
// c00003bc ;
// c00003bc ; Local registers:
// c00003bc ; R24: pointer to UserSwapSpace to save changed registers
// c00003bc ; R25: result sign + manipulations of OpCode + SR
// c00003bc ; R26: OpCode of unimplemented instruction
// c00003bc ; R27: Operand1 of instruction + branch table computation
// c00003bc ; R28: Tmp
// c00003bc ; R29: Operand2 of instruction
// c00003bc ; R30: High-word result
// c00003bc ; R31: Low-word result
// c00003bc ;
// c00003bc ;OS-Vek Bt UnImpISrv ; branch to UnImpl-Ins int server
// c00003bc ;OS-Vek LDH R28, RegSwpUsr ; pointer to RegisterSwapRAM
44E70080 // c00003bc UnImpISrv: OR R28, R28, RegSwpUsr & $1FFF ; load temporarily in R28
// c00003c0
// c00003c0 ; save user register (outside overlay set)
2EC70018 // c00003c0 ST.q R24, R28, 24*4 ; user register
2ECF0019 // c00003c4 ST.q R25, R28, 25*4 ; save
2ED7001A // c00003c8 ST.q R26, R28, 26*4 ; part
2EDF001B // c00003cc ST.q R27, R28, 27*4 ; (I)
// c00003d0
// c00003d0 ; load opcode of not implemented instruction
EAD34000 // c00003d0 LRFS R26, ECADR ; save interrupt address
0FD68000 // c00003d4 LD.q R26, R26, R00 ; load instruction into R26
// c00003d8
// c00003d8 ; save user register
61C0001C // c00003d8 MOV R24, R28 ; copy pointer or R28 to R24
// c00003dc ; switch to user mode
EAC8C000 // c00003dc LRFS R25, SR ; deselect overlay register set
48CE4020 // c00003e0 XOR R25, R25, %00100000 ; by disabling
EB180019 // c00003e4 SRIS SR, R25 ; exception EC status
// c00003e8 ; save user register (within overlay set)
2EE6001C // c00003e8 ST.q R28, R24, 28*4 ; save
2EEE001D // c00003ec ST.q R29, R24, 29*4 ; user register
2EF6001E // c00003f0 ST.q R30, R24, 30*4 ; part
2EFE001F // c00003f4 ST.q R31, R24, 31*4 ; (II)
// c00003f8 ; switch back to EXCP mode
48CE4020 // c00003f8 XOR R25, R25, %00100000 ; select overlay register set
EB180019 // c00003fc SRIS SR, R25 ; by reactivation of EC status
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