📄 4_1vos
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61D80000 // c0000108 CLR R27 ; clear R27
61D00000 // c000010c CLR R26 ; clear R26
61C80000 // c0000110 CLR R25 ; clear R25
61C00000 // c0000114 CLR R24 ; clear R24
61B80000 // c0000118 CLR R23 ; clear R23
61B00000 // c000011c CLR R22 ; clear R22
61A80000 // c0000120 CLR R21 ; clear R21
61A00000 // c0000124 CLR R20 ; clear R20
61980000 // c0000128 CLR R19 ; clear R19
61900000 // c000012c CLR R18 ; clear R18
61880000 // c0000130 CLR R17 ; clear R17
61800000 // c0000134 CLR R16 ; clear R16
61780000 // c0000138 CLR R15 ; clear R15
61700000 // c000013c CLR R14 ; clear R14
61680000 // c0000140 CLR R13 ; clear R13
61600000 // c0000144 CLR R12 ; clear R12
61580000 // c0000148 CLR R11 ; clear R11
61500000 // c000014c CLR R10 ; clear R10
61480000 // c0000150 CLR R09 ; clear R09
61400000 // c0000154 CLR R08 ; clear R08
61380000 // c0000158 CLR R07 ; clear R07
61300000 // c000015c CLR R06 ; clear R06
61280000 // c0000160 CLR R05 ; clear R05
61200000 // c0000164 CLR R04 ; clear R04
61180000 // c0000168 CLR R03 ; clear R03
61100000 // c000016c CLR R02 ; clear R02
61080000 // c0000170 CLR R01 ; clear R01
// c0000174
// c0000174 ; Branch to user program
// c0000174 ; prepare user mode operation
EB300000 // c0000174 SRIS HISR, R00 ; set HW-Int-SR for user mode
EB480000 // c0000178 SRIS HIRPC, R00 ; set HW-Int-RPC to beginning of user RAM
FE000000 // c000017c RETI ; branch to user program
E7000000 // c0000180 CLC ; clear cache
// c0000184
// c0000184
// c0000184
// c0000184
// c0000184
// c0000184 ;##############################################################################
// c0000184 ;
// c0000184 ; I N T E R R U P T V E C T O R
// c0000184 ;
XXXXXXXX // c0000184 org $C0000200
XXXXXXXX // c0000188
XXXXXXXX // c000018c
XXXXXXXX // c0000190
XXXXXXXX // c0000194
XXXXXXXX // c0000198
XXXXXXXX // c000019c
XXXXXXXX // c00001a0
XXXXXXXX // c00001a4
XXXXXXXX // c00001a8
XXXXXXXX // c00001ac
XXXXXXXX // c00001b0
XXXXXXXX // c00001b4
XXXXXXXX // c00001b8
XXXXXXXX // c00001bc
XXXXXXXX // c00001c0
XXXXXXXX // c00001c4
XXXXXXXX // c00001c8
XXXXXXXX // c00001cc
XXXXXXXX // c00001d0
XXXXXXXX // c00001d4
XXXXXXXX // c00001d8
XXXXXXXX // c00001dc
XXXXXXXX // c00001e0
XXXXXXXX // c00001e4
XXXXXXXX // c00001e8
XXXXXXXX // c00001ec
XXXXXXXX // c00001f0
XXXXXXXX // c00001f4
XXXXXXXX // c00001f8
XXXXXXXX // c00001fc
// c0000200
// c0000200 ;------------------------------------------------------------------------------
// c0000200 ; The interrupt vector begins at address IntVektor. For each entry, two lines
// c0000200 ; are reserved. There are 32 different interrupts. The vector is 256 bytes.
// c0000200
// c0000200 ; === Hardware interrupts =====================================================
// c0000200 ; Bus error INT # 00, HWI # 00
FC780040 // c0000200 IntVektor: Bt NotSpIntSrv ; INT not supported by OS
60E00000 // c0000204 MOV R28, 00*4 ; store INT-ID (*4)
// c0000208
// c0000208 ; Page fault INT # 01, HWI # 01
FC78004A // c0000208 Bt PgFltISrv ; branch to page fault int server
EAE30000 // c000020c LRFS R28, HIADR ; load page fault address
// c0000210
// c0000210 ; Misalign INT # 02, HWI # 02
FC78003C // c0000210 Bt NotSpIntSrv ; INT not supported by OS
60E00008 // c0000214 MOV R28, 02*4 ; store INT-ID (*4)
// c0000218
// c0000218 ; Timer event INT # 03, HWI # 03
FC78003A // c0000218 Bt NotSpIntSrv ; INT not supported by OS
60E0000C // c000021c MOV R28, 03*4 ; store INT-ID (*4)
// c0000220
// c0000220 ; INT # 04, HWI # 04
FC780038 // c0000220 Bt NotSpIntSrv ; INT not supported by OS
60E00010 // c0000224 MOV R28, 04*4 ; store INT-ID (*4)
// c0000228
// c0000228 ; INT # 05, HWI # 05
FC780036 // c0000228 Bt NotSpIntSrv ; INT not supported by OS
60E00014 // c000022c MOV R28, 05*4 ; store INT-ID (*4)
// c0000230
// c0000230 ; INT # 06, HWI # 06
FC780034 // c0000230 Bt NotSpIntSrv ; INT not supported by OS
60E00018 // c0000234 MOV R28, 06*4 ; store INT-ID (*4)
// c0000238
// c0000238 ; INT # 07, HWI # 07
FC780032 // c0000238 Bt NotSpIntSrv ; INT not supported by OS
60E0001C // c000023c MOV R28, 07*4 ; store INT-ID (*4)
// c0000240
// c0000240 ; === Execptions ==============================================================
// c0000240 ; CTR after CTR INT # 08, EXC # 00
FC780030 // c0000240 Bt NotSpIntSrv ; INT not supported by OS
60E00020 // c0000244 MOV R28, 08*4 ; store INT-ID (*4)
// c0000248
// c0000248 ; Privilege violation INT # 09, EXC # 01
FC78002E // c0000248 Bt NotSpIntSrv ; INT not supported by OS
60E00024 // c000024c MOV R28, 09*4 ; store INT-ID (*4)
// c0000250
// c0000250 ; Illegal instruction INT # 10, EXC # 02
FC78002C // c0000250 Bt NotSpIntSrv ; INT not supported by OS
60E00028 // c0000254 MOV R28, 10*4 ; store INT-ID (*4)
// c0000258
// c0000258 ; Unimplemented instruction INT # 11, EXC # 03
FC780059 // c0000258 Bt UnImpISrv ; branch to UnImpl-Ins int server
E0E20000 // c000025c LDH R28, RegSwpUsr28 ; INT not supported
// c0000260
// c0000260 ; Division by zero INT # 12, EXC # 04
FC780028 // c0000260 DivByZero: Bt NotSpIntSrv ; INT not supported by OS
60E00030 // c0000264 MOV R28, 12*4 ; store INT-ID (*4)
// c0000268
// c0000268 ; INT # 13, EXC # 05
FC780026 // c0000268 Bt NotSpIntSrv ; INT not supported by OS
60E00034 // c000026c MOV R28, 13*4 ; store INT-ID (*4)
// c0000270
// c0000270 ; INT # 14, EXC # 06
FC780024 // c0000270 Bt NotSpIntSrv ; INT not supported by OS
60E00038 // c0000274 MOV R28, 14*4 ; store INT-ID (*4)
// c0000278
// c0000278 ; PANIC INT # 15, EXC # 07
FC780022 // c0000278 Bt NotSpIntSrv ; INT not supported by OS
60E0003C // c000027c MOV R28, 15*4 ; store INT-ID (*4)
// c0000280
// c0000280 ; === Software interrupts =====================================================
// c0000280 ; INT # 16, SWI # 00
FC780020 // c0000280 Bt NotSpIntSrv ; INT not supported by OS
60E00040 // c0000284 MOV R28, 16*4 ; store INT-ID (*4)
// c0000288
// c0000288 ; Timer control request INT # 17, SWI # 01
FC78002F // c0000288 Bt SWI01Srv ; branch to SWI01 int server
E0E40000 // c000028c LDH R28, TIMER ; load High-Adr timer
// c0000290
// c0000290 ; New interrupt vector INT # 18, SWI # 02
FC780032 // c0000290 Bt SWI02Srv ; branch to SWI02 int server
E0E20000 // c0000294 LDH R28, AddIntSrv ; load address of additional int server
// c0000298
// c0000298 ; Kernel mode request INT # 19, SWI # 03
FC78003C // c0000298 Bt SWI03Srv ; branch to SWI03 int server
EAE20000 // c000029c LRFS R28, SISR ;
// c00002a0
// c00002a0 ; ClockTime request INT # 20, SWI # 04
FC78003E // c00002a0 Bt SWI04Srv ; branch to SWI04 int server
E0E40000 // c00002a4 LDH R28, CLKTM ; address of CLKTM
// c00002a8
// c00002a8 ; INT # 21, SWI # 05
FC780016 // c00002a8 Bt NotSpIntSrv ; INT not supported by OS
60E00054 // c00002ac MOV R28, 21*4 ; store INT-ID (*4)
// c00002b0
// c00002b0 ; INT # 22, SWI # 06
FC780014 // c00002b0 Bt NotSpIntSrv ; INT not supported by OS
60E00058 // c00002b4 MOV R28, 22*4 ; store INT-ID (*4)
// c00002b8
// c00002b8 ; INT # 23, SWI # 07
FC780012 // c00002b8 Bt NotSpIntSrv ; INT not supported by OS
60E0005C // c00002bc MOV R28, 23*4 ; store INT-ID (*4)
// c00002c0
// c00002c0 ; INT # 24, SWI # 08
FC780010 // c00002c0 Bt NotSpIntSrv ; INT not supported by OS
60E00060 // c00002c4 MOV R28, 24*4 ; store INT-ID (*4)
// c00002c8
// c00002c8 ; INT # 25, SWI # 09
FC78000E // c00002c8 Bt NotSpIntSrv ; INT not supported by OS
60E00064 // c00002cc MOV R28, 25*4 ; store INT-ID (*4)
// c00002d0
// c00002d0 ; INT # 26, SWI # 10
FC78000C // c00002d0 Bt NotSpIntSrv ; INT not supported by OS
60E00068 // c00002d4 MOV R28, 26*4 ; store INT-ID (*4)
// c00002d8
// c00002d8 ; INT # 27, SWI # 11
FC78000A // c00002d8 Bt NotSpIntSrv ; INT not supported by OS
60E0006C // c00002dc MOV R28, 27*4 ; store INT-ID (*4)
// c00002e0
// c00002e0 ; INT # 28, SWI # 12
FC780008 // c00002e0 Bt NotSpIntSrv ; INT not supported by OS
60E00070 // c00002e4 MOV R28, 28*4 ; store INT-ID (*4)
// c00002e8
// c00002e8 ; INT # 29, SWI # 13
FC780006 // c00002e8 Bt NotSpIntSrv ; INT not supported by OS
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