📄 4_1vos
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// 00000000 ; VOS Verilog operating system of TOOBSIE
// 00000000 ; Version 2.2
// 00000000 ;------------------------------------------------------------------------------
// 00000000 ; VOS supports test program execution as follows:
// 00000000 ; 1. Switch to user program after reset
// 00000000 ; 2. Handling of interrupts
// 00000000 ;------------------------------------------------------------------------------
// 00000000 ; OS version: B-S-0022
// 00000000 OS_Vers equ $42530022
// 00000000 ;------------------------------------------------------------------------------
// 00000000 ; Important data structures
// 00000000 ; -------------------------
// 00000000 ;
// 00000000 ;
// 00000000 ; Registers
// 00000000 ; =========
// 00000000 ;
// 00000000 ; SR (status register) of CPU
// 00000000 ; Bit 0: Carry Flag \
// 00000000 ; Bit 1: Overflow Flag | Flags
// 00000000 ; Bit 2: Zero Flag |
// 00000000 ; Bit 3: Negative Flag /
// 00000000 ; Bit 4: SWI Status \
// 00000000 ; Bit 5: EXC Status | Mode
// 00000000 ; Bit 6: HWI Status |
// 00000000 ; Bit 7: Kernel/User Status /
// 00000000 ;
// 00000000 ;
// 00000000 ;
// 00000000 ; Memory structure as assumed by VOS
// 00000000 ; ==================================
// 00000000 ;
// 00000000 ; Bank Address After 1st access to bank 3 After RESET
// 00000000 ;
// 00000000 ; 0 $00000000 RAM (USER access to ROM (KERNEL access only)
// 00000000 ; \{$3FFFFFFF\} allowed pages only)
// 00000000 ;
// 00000000 ; 1 $40000000 RAM (KERNEL access only) RAM (KERNEL access only)
// 00000000 ; \{$7FFFFFFF\}
// 00000000 ;
// 00000000 ; 2 $80000000 I/O (KERNEL access only) I/O (KERNEL access only)
// 00000000 ; \{$BFFFFFFF\}
// 00000000 ;
// 00000000 ; 3 $C0000000 ROM (KERNEL access only) ROM (KERNEL access only)
// 00000000 ; \{$FFFFFFFF\}
// 00000000 ;
// 00000000 ;
// 00000000 ;
// 00000000 ; Kernel RAM
// 00000000 ; ==========
// 00000000 ;
// 00000000 ; Start address of interrupt routines
// 00000000 ; Adr: $40000000-$4000007F; Length 128 bytes
// 00000000 ; Function: For each of 32 possible interrupts, a starting address of an
// 00000000 ; associated interrupt routine may be defined:
// 00000000 ; -2, -3, -4 the interrupt is not supported
// 00000000 ; -1 the interrupt is supported directly by OS
// 00000000 ; else starting address of handling routine.
// 00000000 ; If the interrupt is not supported, the "last chance" is checked.
// 00000000 ; If also this case is not supported, the OS produces a HALT.
// 00000000 ; Explanation: For test purposes, additional interrupt servers may be installed.
// 00000000 AddIntSrv equ $40000000
// 00000000 ;
// 00000000 ; Register swap RAM
// 00000000 ; Adr: $40000084-$400000FF User: R01..R31 32*4Byte=128
// 00000000 ; Adr: $40000100-$4000010F Excp/SWI: R28..R31 4*4Byte= 16
// 00000000 ; Adr: $40000110-$4000011F HWI: R28..R31 4*4Byte= 16
// 00000000 ; Adr: $40000120-$40000123 User: RPC 4Byte
// 00000000 ; Adr: $40000124-$40000127 Excp/SWI: RPC 4Byte
// 00000000 ; Adr: $40000128-$4000012B HWI: RPC 4Byte
// 00000000 RegSwpUsr equ $40000080
// 00000000 RegSwpUsr01 equ $40000084
// 00000000 RegSwpUsr28 equ $400000F0
// 00000000 RegSwpExc equ $40000100
// 00000000 RegSwpHWI equ $40000110
// 00000000 RegRPCUsr equ $40000120
// 00000000 RegRPCExc equ $40000124
// 00000000 RegRPCHWI equ $40000128
// 00000000 ;
// 00000000 ;
// 00000000 ;
// 00000000 ; I/O area
// 00000000 ; ========
// 00000000 ;
// 00000000 ; HWPD (hardware page daemon) memory mapped
// 00000000 ; Adr: $80000000
// 00000000 ; Function: The HWPD is organized as a FIFO. The page adress is stored.
// 00000000 ; The last 3 pages are stored. The "byte address" of the page
// 00000000 ; is stored. The least siginifcant address byte is ignored.
// 00000000 HWPD equ $80000000
// 00000000 ;
// 00000000 ;
// 00000000 ; TIMER (hardware component) memory mapped
// 00000000 ; Adr: $80000004
// 00000000 ; Function: The timer triggers an interrupt after a preset time.
// 00000000 TIMER equ $80000004
// 00000000 ;
// 00000000 ;
// 00000000 ; CLKTM (hardware component) memory mapped
// 00000000 ; Adr: $80000008
// 00000000 ; Function: CLKTM counts the clock since start of system.
// 00000000 ; This number can be read
// 00000000 CLKTM equ $80000008
// 00000000
// 00000000
// 00000000
// 00000000
// 00000000 ;##############################################################################
// 00000000 ;
// 00000000 ; Begin of operating system
// 00000000 ;
// 00000000 org2 $C0000000
// c0000000
// c0000000 ;------------------------------------------------------------------------------
// c0000000 ; First, the ROM with address 0 is selected. Only when an address after
// c0000000 ; $C0000000 is explicitly given, the RAM with the user program is selected
// c0000000 ; instead of the ROMs.
B0000002 // c0000000 RESET: CALL ForceSwitch ; address access from $C0000000
// c0000004
// c0000004 ; Set VBR to interrupt vector
E00E0000 // c0000004 LDH R01, IntVektor ; load High-Adr
44084200 // c0000008 ForceSwitch:OR R01, R01, IntVektor & $1FFF ; load Low-Adr
EB280001 // c000000c SRIS VBR, R01 ; store Adr in VBR
// c0000010
// c0000010 ; configure additional interrupt server
E0220000 // c0000010 LDH R04, AddIntSrv ; load High-Adr
44210000 // c0000014 OR R04, R04, AddIntSrv & $1FFF ; load Low-Adr
// c0000018 ;
// c0000018 ; INTs supported directly by OS may be disabled here by -1
60083FFF // c0000018 MOV R01, -1 ; disable
60103FFE // c000001c MOV R02, -2 ; enable
// c0000020 ; optionally minimal support for timer events
E01E0000 // c0000020 LDH R03, TimerEvSrv ; load High-Adr
4418C350 // c0000024 OR R03, R03, TimerEvSrv & $1FFF ; load Low-Adr
// c0000028 ;
2E110000 // c0000028 ST.q R02, R04, $00 ; bus error not supported
2E090001 // c000002c ST.q R01, R04, $04 ; page fault supported
2E110002 // c0000030 ST.q R02, R04, $08 ; misalign not supported
2E190003 // c0000034 ST.q R03, R04, $0C ; HWI#3 optionally supported
2E110004 // c0000038 ST.q R02, R04, $10 ; HWI#4 not supported
2E110005 // c000003c ST.q R02, R04, $14 ; HWI#5 not supported
2E110006 // c0000040 ST.q R02, R04, $18 ; HWI#6 not supported
2E110007 // c0000044 ST.q R02, R04, $1C ; HWI#7 not supported
2E110008 // c0000048 ST.q R02, R04, $20 ; CTR after CTR not supported
2E110009 // c000004c ST.q R02, R04, $24 ; PrivVioalation not supported
2E11000A // c0000050 ST.q R02, R04, $28 ; illegal instr. not supported
2E09000B // c0000054 ST.q R01, R04, $2C ; unimpl. instr. supported
2E11000C // c0000058 ST.q R02, R04, $30 ; EXC#4 not supported
2E11000D // c000005c ST.q R02, R04, $34 ; EXC#5 not supported
2E11000E // c0000060 ST.q R02, R04, $38 ; EXC#6 not supported
2E11000F // c0000064 ST.q R02, R04, $3C ; EXC#7 not supported
2E110010 // c0000068 ST.q R02, R04, $40 ; SWI#0 not supported
2E090011 // c000006c ST.q R01, R04, $44 ; SWI#1 supported
2E090012 // c0000070 ST.q R01, R04, $48 ; SWI#2 supported
2E090013 // c0000074 ST.q R01, R04, $4C ; SWI#3 supported
2E090014 // c0000078 ST.q R01, R04, $50 ; SWI#4 supported
2E110015 // c000007c ST.q R02, R04, $54 ; SWI#5 not supported
2E110016 // c0000080 ST.q R02, R04, $58 ; SWI#6 not supported
2E110017 // c0000084 ST.q R02, R04, $5C ; SWI#7 not supported
2E110018 // c0000088 ST.q R02, R04, $60 ; SWI#8 not supported
2E110019 // c000008c ST.q R02, R04, $64 ; SWI#9 not supported
2E11001A // c0000090 ST.q R02, R04, $68 ; SWI#10 not supported
2E11001B // c0000094 ST.q R02, R04, $6C ; SWI#11 not supported
2E11001C // c0000098 ST.q R02, R04, $70 ; SWI#12 not supported
2E11001D // c000009c ST.q R02, R04, $74 ; SWI#13 not supported
2E11001E // c00000a0 ST.q R02, R04, $78 ; SWI#14 not supported
2E09001F // c00000a4 ST.q R01, R04, $7C ; SWI#15 supported
2E110020 // c00000a8 ST.q R02, R04, $80 ; "last chance" not supported
// c00000ac
// c00000ac ; Initialize HWPD and store first user page.
// c00000ac ; The first page is stored 3 times for a correct setup.
E00C0000 // c00000ac LDH R01, HWPD ; load High-Adr
44084000 // c00000b0 OR R01, R01, HWPD & $1FFF ; load Low-Adr
2E004000 // c00000b4 ST.q R00, R01, 0 ; store page 0
2E004000 // c00000b8 ST.q R00, R01, 0 ; store page 0
2E004000 // c00000bc ST.q R00, R01, 0 ; store page 0
// c00000c0
// c00000c0 ; To support comparison of test results, all regular registers are initialized,
// c00000c0 ; otherwise, the signature would differ.
// c00000c0 ; User mode
60080080 // c00000c0 MOV R01, %10000000 ; set user mode and select register set
EB180001 // c00000c4 SRIS SR, R01 ;
61F80000 // c00000c8 CLR R31 ; clear R31
61F00000 // c00000cc CLR R30 ; clear R30
61E80000 // c00000d0 CLR R29 ; clear R29
61E00000 // c00000d4 CLR R28 ; clear R28
// c00000d8 ; Excp/SWI mode
600800B0 // c00000d8 MOV R01, %10110000 ; set Excp/SWI mode and select
EB180001 // c00000dc SRIS SR, R01 ; overlay register set
61F80000 // c00000e0 CLR R31 ; clear R31
61F00000 // c00000e4 CLR R30 ; clear R30
61E80000 // c00000e8 CLR R29 ; clear R29
61E00000 // c00000ec CLR R28 ; clear R28
// c00000f0 ; HWI mode
600800C0 // c00000f0 MOV R01, %11000000 ; set HWI mode and select
EB180001 // c00000f4 SRIS SR, R01 ; overlay register set
61F80000 // c00000f8 CLR R31 ; clear R31
61F00000 // c00000fc CLR R30 ; clear R30
61E80000 // c0000100 CLR R29 ; clear R29
61E00000 // c0000104 CLR R28 ; clear R28
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