4_3test

大型risc处理器设计源代码,这是书中的代码 基于流水线的risc cpu设计

//----------------------------------------------------------------------------   t0000
//                                                                               t0001
// TEST                                                                          t0002
//                                                                               t0003
// Control file for simulation                                                   t0004
//                                                                               t0005
//----------------------------------------------------------------------------   t0006
                                                                                 t0007
`define TRACE         0       // instructions                                    t0008
`define STATISTICS    0       // statistics at the end                           t0009
`define DUMP          1       // hex-dump                                        t0010
`define STEP          0       // dump in single step mode                        t0011
`define EXTRACE       0       // dump after every instruction                    t0012
`define MEMDUMP       1       // system memory dump                              t0013
`define REGDUMP       1       // register dump                                   t0014
`define BTCDUMP       0       // BTC dump                                        t0015
`define MPCDUMP       0       // MPC dump                                        t0016
`define MDUMPLO  'h0000       // memory dump: first address                      t0017
`define MDUMPHI  'h01ff       // memory dump: last address                       t0018
`define WAVES         0       // graphwaves                                      t0019
`define REGS          0       // not supported                                   t0020
                                                                                 t0021
// System                                                                        t0022
`define PROTOCOL                 0 // bus protocol: 1=synchronous, 0=asynchronoust0023
`define QUAD_CYCLE              25 // clock period / 4                           t0024
`define RESET_TIME             525 // reset pulse length                         t0025
`define MAX_CYCLES          500000 // maximum number of clock cycles             t0026
`define MHS_TIME                80 // MHS pulse length without wait states       t0027
`define PROGRAM "factoria.exe"     // RAM: initial file                          t0028
`define OS_ROM  "vos.exe"          // operating system ROM: initial file         t0029
`define PRG_FORMAT               1 // format of user program:     0=binary, 1=hext0030
`define OS_FORMAT                1 // format of operating system: 0=binary, 1=hext0031
`define USER_RAM_SIZE           13 // number of word address bits (13=32KB)      t0032
`define KERNEL_RAM_SIZE         13 // number of word address bits (13=32KB)      t0033
`define ROM_SIZE                10 // number of word address bits (10= 4KB)      t0034
`define RAMTIME                 60 // RAM access time                            t0035
`define ROMTIME                 60 // ROM access time                            t0036
`define WAITSTATE      8'b00000000 // wait states for memory accesses            t0037
`define PAGEFAULTS               0 // page fault requests: 0=no, 1=yes           t0038
`define DMAILEAVE                0 // DMA interleave: 0=no, 1=yes                t0039
`define CHK_EN                   1 // checking: 0=off, 1=on                      t0040
`define CHK_STP_EN               0 // stop, if checking error: 0=off, 1=on       t0041
`define CHK_HGH_BITs             1 // check high bits (ADDR[29:..]): 0=off, 1=on t0042
                                   // <=> RAM not "cyclic"                       t0043
                                                                                 t0044
// Cache mode                                                                    t0045
`define SERIAL_MODE   1'b0   // 0=parallel mode, 1=serial mode                   t0046
`define EN_MEM_BRK    1'b1   // MEMBRK for asynchronous bus protocol             t0047
`define IC_MODE       1'b1   // instruction cache mode: 0=off, 1=on              t0048
`define RIB_MODE      1'b0   // reduced instruction buffer mode: 0=off, 1=on     t0049
`define BTC_CALL      1'b1   // store CALLs in BTC                               t0050
`define BTC_BCC       1'b1   // store BCCs in BTC                                t0051
                                                                                 t0052
// Register transfer delay in simulation time units                              t0053
`define DELTA     1                                                              t0054
                                                                                 t0055
// Delay for nMRQ after rising clock edge (> DELTA)                              t0056
`define BCUDELAY  2                                                              t0057