lvds_tx.bsf

Altera FPGA CPLD设计高级篇电子书籍

/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2004 Altera Corporation
Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
support information,  device programming or simulation file,  and any other
associated  documentation or information  provided by  Altera  or a partner
under  Altera's   Megafunction   Partnership   Program  may  be  used  only
to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
other  use  of such  megafunction  design,  netlist,  support  information,
device programming or simulation file,  or any other  related documentation
or information  is prohibited  for  any  other purpose,  including, but not
limited to  modification,  reverse engineering,  de-compiling, or use  with
any other  silicon devices,  unless such use is  explicitly  licensed under
a separate agreement with  Altera  or a megafunction partner.  Title to the
intellectual property,  including patents,  copyrights,  trademarks,  trade
secrets,  or maskworks,  embodied in any such megafunction design, netlist,
support  information,  device programming or simulation file,  or any other
related documentation or information provided by  Altera  or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.
*/
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(symbol
	(rect 0 0 288 160)
	(text "lvds_tx" (rect 124 1 171 17)(font "Arial" (font_size 10)))
	(text "inst" (rect 8 144 25 156)(font "Arial" ))
	(port
		(pt 0 32)
		(input)
		(text "tx_in[15..0]" (rect 0 0 62 14)(font "Arial" (font_size 8)))
		(text "tx_in[15..0]" (rect 4 19 57 32)(font "Arial" (font_size 8)))
		(line (pt 0 32)(pt 80 32)(line_width 3))
	)
	(port
		(pt 0 48)
		(input)
		(text "tx_inclock" (rect 0 0 56 14)(font "Arial" (font_size 8)))
		(text "tx_inclock" (rect 4 35 50 48)(font "Arial" (font_size 8)))
		(line (pt 0 48)(pt 96 48)(line_width 1))
	)
	(port
		(pt 288 48)
		(output)
		(text "tx_outclock" (rect 0 0 64 14)(font "Arial" (font_size 8)))
		(text "tx_outclock" (rect 230 35 282 48)(font "Arial" (font_size 8)))
		(line (pt 288 48)(pt 216 48)(line_width 1))
	)
	(port
		(pt 288 32)
		(output)
		(text "tx_out[1..0]" (rect 0 0 63 14)(font "Arial" (font_size 8)))
		(text "tx_out[1..0]" (rect 231 19 284 32)(font "Arial" (font_size 8)))
		(line (pt 288 32)(pt 216 32)(line_width 3))
	)
	(drawing
		(text "LVDS Transmitter" (rect 119 42 193 54)(font "Arial" ))
		(text "2 channels, x8" (rect 126 58 187 70)(font "Arial" ))
		(text "105.00 MHz" (rect 132 74 181 86)(font "Arial" ))
		(text "O/P data rate=840.00" (rect 112 90 201 102)(font "Arial" ))
		(text "CoreClk Freq=105.00" (rect 112 106 201 118)(font "Arial" ))
		(text "Outclk Freq = 105.00" (rect 112 122 200 134)(font "Arial" ))
		(text "Stratix" (rect 253 146 280 158)(font "Arial" ))
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)