📄 diff_io_top.vwf

📁 Altera FPGA CPLD设计高级篇电子书籍
💻 VWF
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}

TRANSITION_LIST("lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rxreg[9]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 400.0;
	}
}

TRANSITION_LIST("lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rxreg[10]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 400.0;
	}
}

TRANSITION_LIST("lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rxreg[11]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 400.0;
	}
}

TRANSITION_LIST("lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rxreg[12]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 400.0;
	}
}

TRANSITION_LIST("lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rxreg[13]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 400.0;
	}
}

TRANSITION_LIST("lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rxreg[14]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 400.0;
	}
}

TRANSITION_LIST("lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rxreg[15]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 400.0;
	}
}

TRANSITION_LIST("lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 400.0;
	}
}

TRANSITION_LIST("lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 400.0;
	}
}

TRANSITION_LIST("lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 400.0;
	}
}

TRANSITION_LIST("lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 400.0;
	}
}

TRANSITION_LIST("lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[4]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 400.0;
	}
}

TRANSITION_LIST("lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[5]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 400.0;
	}
}

TRANSITION_LIST("lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[6]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 400.0;
	}
}

TRANSITION_LIST("lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[7]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 400.0;
	}
}

TRANSITION_LIST("lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[8]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 400.0;
	}
}

TRANSITION_LIST("lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[9]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 400.0;
	}
}

TRANSITION_LIST("lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[10]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 400.0;
	}
}

TRANSITION_LIST("lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[11]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 400.0;
	}
}

TRANSITION_LIST("lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[12]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 400.0;
	}
}

TRANSITION_LIST("lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[13]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 400.0;
	}
}

TRANSITION_LIST("lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[14]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 400.0;
	}
}

TRANSITION_LIST("lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[15]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 400.0;
	}
}

DISPLAY_LINE
{
	CHANNEL = "rx_data_align";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 0;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "rx_in[0]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 1;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "rx_in[1]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 2;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "rx_inclock";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 3;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "a";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 4;
	TREE_LEVEL = 0;
	CHILDREN = 5, 6, 7, 8, 9, 10, 11, 12;
}

DISPLAY_LINE
{
	CHANNEL = "lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rxreg[15]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 5;
	TREE_LEVEL = 1;
	PARENT = 4;
}

DISPLAY_LINE
{
	CHANNEL = "lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rxreg[14]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 6;
	TREE_LEVEL = 1;
	PARENT = 4;
}

DISPLAY_LINE
{
	CHANNEL = "lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rxreg[13]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 7;
	TREE_LEVEL = 1;
	PARENT = 4;
}

DISPLAY_LINE
{
	CHANNEL = "lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rxreg[12]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 8;
	TREE_LEVEL = 1;
	PARENT = 4;
}

DISPLAY_LINE
{
	CHANNEL = "lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rxreg[11]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 9;
	TREE_LEVEL = 1;
	PARENT = 4;
}

DISPLAY_LINE
{
	CHANNEL = "lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rxreg[10]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 10;
	TREE_LEVEL = 1;
	PARENT = 4;
}

DISPLAY_LINE
{
	CHANNEL = "lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rxreg[9]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 11;
	TREE_LEVEL = 1;
	PARENT = 4;
}

DISPLAY_LINE
{
	CHANNEL = "lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rxreg[8]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 12;
	TREE_LEVEL = 1;
	PARENT = 4;
}

DISPLAY_LINE
{
	CHANNEL = "b";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 13;
	TREE_LEVEL = 0;
	CHILDREN = 14, 15, 16, 17, 18, 19, 20, 21;
}

DISPLAY_LINE
{
	CHANNEL = "lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rxreg[7]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 14;
	TREE_LEVEL = 1;
	PARENT = 13;
}

DISPLAY_LINE
{
	CHANNEL = "lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rxreg[6]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 15;
	TREE_LEVEL = 1;
	PARENT = 13;
}

DISPLAY_LINE
{
	CHANNEL = "lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rxreg[5]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 16;
	TREE_LEVEL = 1;
	PARENT = 13;
}

DISPLAY_LINE
{
	CHANNEL = "lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rxreg[4]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 17;
	TREE_LEVEL = 1;
	PARENT = 13;
}

DISPLAY_LINE
{
	CHANNEL = "lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rxreg[3]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 18;
	TREE_LEVEL = 1;
	PARENT = 13;
}

DISPLAY_LINE
{
	CHANNEL = "lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rxreg[2]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 19;
	TREE_LEVEL = 1;
	PARENT = 13;
}

DISPLAY_LINE
{
	CHANNEL = "lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rxreg[1]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 20;
	TREE_LEVEL = 1;
	PARENT = 13;
}

DISPLAY_LINE
{
	CHANNEL = "lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rxreg[0]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 21;
	TREE_LEVEL = 1;
	PARENT = 13;
}

DISPLAY_LINE
{
	CHANNEL = "lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 22;
	TREE_LEVEL = 0;
	CHILDREN = 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38;
}

DISPLAY_LINE
{
	CHANNEL = "lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[15]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 23;
	TREE_LEVEL = 1;
	PARENT = 22;
}

DISPLAY_LINE
{
	CHANNEL = "lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[14]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 24;
	TREE_LEVEL = 1;
	PARENT = 22;
}

DISPLAY_LINE
{
	CHANNEL = "lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[13]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 25;
	TREE_LEVEL = 1;
	PARENT = 22;
}

DISPLAY_LINE
{
	CHANNEL = "lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[12]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 26;
	TREE_LEVEL = 1;
	PARENT = 22;
}

DISPLAY_LINE
{
	CHANNEL = "lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[11]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 27;
	TREE_LEVEL = 1;
	PARENT = 22;
}

DISPLAY_LINE
{
	CHANNEL = "lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[10]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 28;
	TREE_LEVEL = 1;
	PARENT = 22;
}

DISPLAY_LINE
{
	CHANNEL = "lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[9]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 29;
	TREE_LEVEL = 1;
	PARENT = 22;
}

DISPLAY_LINE
{
	CHANNEL = "lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[8]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 30;
	TREE_LEVEL = 1;
	PARENT = 22;
}

DISPLAY_LINE
{
	CHANNEL = "lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[7]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 31;
	TREE_LEVEL = 1;
	PARENT = 22;
}

DISPLAY_LINE
{
	CHANNEL = "lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[6]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 32;
	TREE_LEVEL = 1;
	PARENT = 22;
}

DISPLAY_LINE
{
	CHANNEL = "lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[5]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 33;
	TREE_LEVEL = 1;
	PARENT = 22;
}

DISPLAY_LINE
{
	CHANNEL = "lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[4]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 34;
	TREE_LEVEL = 1;
	PARENT = 22;
}

DISPLAY_LINE
{
	CHANNEL = "lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[3]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 35;
	TREE_LEVEL = 1;
	PARENT = 22;
}

DISPLAY_LINE
{
	CHANNEL = "lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[2]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 36;
	TREE_LEVEL = 1;
	PARENT = 22;
}

DISPLAY_LINE
{
	CHANNEL = "lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[1]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 37;
	TREE_LEVEL = 1;
	PARENT = 22;
}

DISPLAY_LINE
{
	CHANNEL = "lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[0]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 38;
	TREE_LEVEL = 1;
	PARENT = 22;
}

TIME_BAR
{
	TIME = 12000;
	MASTER = TRUE;
}
;
上一页 12
💿 文件大小 54407 K
👤 上传用户 myhand123
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🏷️ 相关标签

#Altera #FPGA #CPLD #电子
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