diff_io_top.map.eqn

Altera FPGA CPLD设计高级篇电子书籍

--H1L9Q is mult:mult_inst|altmult_add:ALTMULT_ADD_component|mult_add_v4n1:auto_generated|mac_mult1~DATAOUT8
H1L9Q = H1_mac_mult1_result_reg[8];

--H1L01Q is mult:mult_inst|altmult_add:ALTMULT_ADD_component|mult_add_v4n1:auto_generated|mac_mult1~DATAOUT9
H1L01Q = H1_mac_mult1_result_reg[9];

--H1L11Q is mult:mult_inst|altmult_add:ALTMULT_ADD_component|mult_add_v4n1:auto_generated|mac_mult1~DATAOUT10
H1L11Q = H1_mac_mult1_result_reg[10];

--H1L21Q is mult:mult_inst|altmult_add:ALTMULT_ADD_component|mult_add_v4n1:auto_generated|mac_mult1~DATAOUT11
H1L21Q = H1_mac_mult1_result_reg[11];

--H1L31Q is mult:mult_inst|altmult_add:ALTMULT_ADD_component|mult_add_v4n1:auto_generated|mac_mult1~DATAOUT12
H1L31Q = H1_mac_mult1_result_reg[12];

--H1L41Q is mult:mult_inst|altmult_add:ALTMULT_ADD_component|mult_add_v4n1:auto_generated|mac_mult1~DATAOUT13
H1L41Q = H1_mac_mult1_result_reg[13];

--H1L51Q is mult:mult_inst|altmult_add:ALTMULT_ADD_component|mult_add_v4n1:auto_generated|mac_mult1~DATAOUT14
H1L51Q = H1_mac_mult1_result_reg[14];

--H1L61Q is mult:mult_inst|altmult_add:ALTMULT_ADD_component|mult_add_v4n1:auto_generated|mac_mult1~DATAOUT15
H1L61Q = H1_mac_mult1_result_reg[15];


--E1_rxreg[0] is lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rxreg[0]
--operation mode is normal

E1_rxreg[0]_lut_out = E1_rx[0];
E1_rxreg[0] = DFFEA(E1_rxreg[0]_lut_out, E1_rx_outclock, VCC, , , , );


--E1_rxreg[1] is lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rxreg[1]
--operation mode is normal

E1_rxreg[1]_lut_out = E1L02;
E1_rxreg[1] = DFFEA(E1_rxreg[1]_lut_out, E1_rx_outclock, VCC, , , , );


--E1_rxreg[2] is lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rxreg[2]
--operation mode is normal

E1_rxreg[2]_lut_out = E1L12;
E1_rxreg[2] = DFFEA(E1_rxreg[2]_lut_out, E1_rx_outclock, VCC, , , , );


--E1_rxreg[3] is lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rxreg[3]
--operation mode is normal

E1_rxreg[3]_lut_out = E1L22;
E1_rxreg[3] = DFFEA(E1_rxreg[3]_lut_out, E1_rx_outclock, VCC, , , , );


--E1_rxreg[4] is lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rxreg[4]
--operation mode is normal

E1_rxreg[4]_lut_out = E1L32;
E1_rxreg[4] = DFFEA(E1_rxreg[4]_lut_out, E1_rx_outclock, VCC, , , , );


--E1_rxreg[5] is lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rxreg[5]
--operation mode is normal

E1_rxreg[5]_lut_out = E1L42;
E1_rxreg[5] = DFFEA(E1_rxreg[5]_lut_out, E1_rx_outclock, VCC, , , , );


--E1_rxreg[6] is lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rxreg[6]
--operation mode is normal

E1_rxreg[6]_lut_out = E1L52;
E1_rxreg[6] = DFFEA(E1_rxreg[6]_lut_out, E1_rx_outclock, VCC, , , , );


--E1_rxreg[7] is lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rxreg[7]
--operation mode is normal

E1_rxreg[7]_lut_out = E1L62;
E1_rxreg[7] = DFFEA(E1_rxreg[7]_lut_out, E1_rx_outclock, VCC, , , , );


--E1_rxreg[8] is lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rxreg[8]
--operation mode is normal

E1_rxreg[8]_lut_out = E1_rx[1];
E1_rxreg[8] = DFFEA(E1_rxreg[8]_lut_out, E1_rx_outclock, VCC, , , , );


--E1_rxreg[9] is lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rxreg[9]
--operation mode is normal

E1_rxreg[9]_lut_out = E1L92;
E1_rxreg[9] = DFFEA(E1_rxreg[9]_lut_out, E1_rx_outclock, VCC, , , , );


--E1_rxreg[10] is lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rxreg[10]
--operation mode is normal

E1_rxreg[10]_lut_out = E1L03;
E1_rxreg[10] = DFFEA(E1_rxreg[10]_lut_out, E1_rx_outclock, VCC, , , , );


--E1_rxreg[11] is lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rxreg[11]
--operation mode is normal

E1_rxreg[11]_lut_out = E1L13;
E1_rxreg[11] = DFFEA(E1_rxreg[11]_lut_out, E1_rx_outclock, VCC, , , , );


--E1_rxreg[12] is lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rxreg[12]
--operation mode is normal

E1_rxreg[12]_lut_out = E1L23;
E1_rxreg[12] = DFFEA(E1_rxreg[12]_lut_out, E1_rx_outclock, VCC, , , , );


--E1_rxreg[13] is lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rxreg[13]
--operation mode is normal

E1_rxreg[13]_lut_out = E1L33;
E1_rxreg[13] = DFFEA(E1_rxreg[13]_lut_out, E1_rx_outclock, VCC, , , , );


--E1_rxreg[14] is lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rxreg[14]
--operation mode is normal

E1_rxreg[14]_lut_out = E1L43;
E1_rxreg[14] = DFFEA(E1_rxreg[14]_lut_out, E1_rx_outclock, VCC, , , , );


--E1_rxreg[15] is lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rxreg[15]
--operation mode is normal

E1_rxreg[15]_lut_out = E1L53;
E1_rxreg[15] = DFFEA(E1_rxreg[15]_lut_out, E1_rx_outclock, VCC, , , , );


--E1_rx[0] is lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rx[0]
E1_rx[0] = SERDES_RX.DATAOUT0(.DATAIN(rx_in[0]), .CLK0(E1_pll), .ENABLE0(E1L9), .ENABLE1(E1L01));

--E1L02 is lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rx[0]~DATAOUT1
E1L02 = SERDES_RX.DATAOUT1(.DATAIN(rx_in[0]), .CLK0(E1_pll), .ENABLE0(E1L9), .ENABLE1(E1L01));

--E1L12 is lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rx[0]~DATAOUT2
E1L12 = SERDES_RX.DATAOUT2(.DATAIN(rx_in[0]), .CLK0(E1_pll), .ENABLE0(E1L9), .ENABLE1(E1L01));

--E1L22 is lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rx[0]~DATAOUT3
E1L22 = SERDES_RX.DATAOUT3(.DATAIN(rx_in[0]), .CLK0(E1_pll), .ENABLE0(E1L9), .ENABLE1(E1L01));

--E1L32 is lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rx[0]~DATAOUT4
E1L32 = SERDES_RX.DATAOUT4(.DATAIN(rx_in[0]), .CLK0(E1_pll), .ENABLE0(E1L9), .ENABLE1(E1L01));

--E1L42 is lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rx[0]~DATAOUT5
E1L42 = SERDES_RX.DATAOUT5(.DATAIN(rx_in[0]), .CLK0(E1_pll), .ENABLE0(E1L9), .ENABLE1(E1L01));

--E1L52 is lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rx[0]~DATAOUT6
E1L52 = SERDES_RX.DATAOUT6(.DATAIN(rx_in[0]), .CLK0(E1_pll), .ENABLE0(E1L9), .ENABLE1(E1L01));

--E1L62 is lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rx[0]~DATAOUT7
E1L62 = SERDES_RX.DATAOUT7(.DATAIN(rx_in[0]), .CLK0(E1_pll), .ENABLE0(E1L9), .ENABLE1(E1L01));


--E1_rx[1] is lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rx[1]
E1_rx[1] = SERDES_RX.DATAOUT0(.DATAIN(rx_in[1]), .CLK0(E1_pll), .ENABLE0(E1L9), .ENABLE1(E1L01));

--E1L92 is lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rx[1]~DATAOUT1
E1L92 = SERDES_RX.DATAOUT1(.DATAIN(rx_in[1]), .CLK0(E1_pll), .ENABLE0(E1L9), .ENABLE1(E1L01));

--E1L03 is lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rx[1]~DATAOUT2
E1L03 = SERDES_RX.DATAOUT2(.DATAIN(rx_in[1]), .CLK0(E1_pll), .ENABLE0(E1L9), .ENABLE1(E1L01));

--E1L13 is lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rx[1]~DATAOUT3
E1L13 = SERDES_RX.DATAOUT3(.DATAIN(rx_in[1]), .CLK0(E1_pll), .ENABLE0(E1L9), .ENABLE1(E1L01));

--E1L23 is lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rx[1]~DATAOUT4
E1L23 = SERDES_RX.DATAOUT4(.DATAIN(rx_in[1]), .CLK0(E1_pll), .ENABLE0(E1L9), .ENABLE1(E1L01));

--E1L33 is lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rx[1]~DATAOUT5
E1L33 = SERDES_RX.DATAOUT5(.DATAIN(rx_in[1]), .CLK0(E1_pll), .ENABLE0(E1L9), .ENABLE1(E1L01));

--E1L43 is lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rx[1]~DATAOUT6
E1L43 = SERDES_RX.DATAOUT6(.DATAIN(rx_in[1]), .CLK0(E1_pll), .ENABLE0(E1L9), .ENABLE1(E1L01));

--E1L53 is lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rx[1]~DATAOUT7
E1L53 = SERDES_RX.DATAOUT7(.DATAIN(rx_in[1]), .CLK0(E1_pll), .ENABLE0(E1L9), .ENABLE1(E1L01));


--rx_data_align is rx_data_align
--operation mode is input

rx_data_align = INPUT();


--rx_inclock is rx_inclock
--operation mode is input

rx_inclock = INPUT();


--rx_in[0] is rx_in[0]
--operation mode is input

rx_in[0] = INPUT();


--rx_in[1] is rx_in[1]
--operation mode is input

rx_in[1] = INPUT();


--rx_locked is rx_locked
--operation mode is output

rx_locked = OUTPUT(!E1L61);


--tx_out[1] is tx_out[1]
--operation mode is output

tx_out[1] = OUTPUT(F1_tx_out[1]);


--tx_out[0] is tx_out[0]
--operation mode is output

tx_out[0] = OUTPUT(F1_tx_out[0]);


--tx_outclock is tx_outclock
--operation mode is output

tx_outclock = OUTPUT(F1_tx_outclock);