diff_io_top.tan.rpt

Altera FPGA CPLD设计高级篇电子书籍

+------------------------------------------------------------------+--------------------+------------+------------------+------------+-----------------------+---------------------+----------+
; Clock Node Name                                                  ; Clock Setting Name ; Type       ; Fmax Requirement ; Based on   ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset   ;
+------------------------------------------------------------------+--------------------+------------+------------------+------------+-----------------------+---------------------+----------+
; lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|pll~ENAOUT0 ;                    ; PLL output ; 105.01 MHz       ; rx_inclock ; 1                     ; 1                   ; 0.091 ns ;
; lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|pll~ENAOUT1 ;                    ; PLL output ; 105.01 MHz       ; NONE       ; N/A                   ; N/A                 ; N/A      ;
; lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|pll         ;                    ; PLL output ; 840.34 MHz       ; rx_inclock ; 8                     ; 1                   ; 0.091 ns ;
; lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rx_outclock ;                    ; PLL output ; 105.01 MHz       ; rx_inclock ; 1                     ; 1                   ; 0.091 ns ;
; rx_inclock                                                       ;                    ; User Pin   ; 105.01 MHz       ; NONE       ; N/A                   ; N/A                 ; N/A      ;
+------------------------------------------------------------------+--------------------+------------+------------------+------------+-----------------------+---------------------+----------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|pll~ENAOUT1'                                                                                                                                                                                                                                                                                                                 ;
+----------+----------------------+----------------------------------------------------------------+--------------------------------------------------------------------+------------------------------------------------------------------+------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+
; Slack    ; Actual fmax (period) ; From                                                           ; To                                                                 ; From Clock                                                       ; To Clock                                                         ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+----------+----------------------+----------------------------------------------------------------+--------------------------------------------------------------------+------------------------------------------------------------------+------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+
; 7.287 ns ; None                 ; lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[13] ; lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|tx_out[1]~in5 ; lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rx_outclock ; lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|pll~ENAOUT1 ; 9.432 ns                    ; 8.855 ns                  ; 1.568 ns                ;
; 7.291 ns ; None                 ; lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[7]  ; lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|tx_out[0]~in7 ; lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rx_outclock ; lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|pll~ENAOUT1 ; 9.432 ns                    ; 8.853 ns                  ; 1.562 ns                ;
; 7.301 ns ; None                 ; lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[4]  ; lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|tx_out[0]~in4 ; lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rx_outclock ; lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|pll~ENAOUT1 ; 9.432 ns                    ; 8.853 ns                  ; 1.552 ns                ;
; 7.305 ns ; None                 ; lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[12] ; lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|tx_out[1]~in4 ; lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rx_outclock ; lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|pll~ENAOUT1 ; 9.432 ns                    ; 8.855 ns                  ; 1.550 ns                ;
; 7.306 ns ; None                 ; lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[10] ; lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|tx_out[1]~in2 ; lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rx_outclock ; lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|pll~ENAOUT1 ; 9.432 ns                    ; 8.855 ns                  ; 1.549 ns                ;
; 7.306 ns ; None                 ; lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[2]  ; lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|tx_out[0]~in2 ; lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rx_outclock ; lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|pll~ENAOUT1 ; 9.432 ns                    ; 8.853 ns                  ; 1.547 ns                ;
; 7.306 ns ; None                 ; lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[5]  ; lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|tx_out[0]~in5 ; lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rx_outclock ; lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|pll~ENAOUT1 ; 9.432 ns                    ; 8.853 ns                  ; 1.547 ns                ;
; 7.307 ns ; None                 ; lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[14] ; lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|tx_out[1]~in6 ; lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rx_outclock ; lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|pll~ENAOUT1 ; 9.432 ns                    ; 8.855 ns                  ; 1.548 ns                ;
; 7.308 ns ; None                 ; lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[3]  ; lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|tx_out[0]~in3 ; lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rx_outclock ; lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|pll~ENAOUT1 ; 9.432 ns                    ; 8.853 ns                  ; 1.545 ns                ;
; 7.309 ns ; None                 ; lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[0]  ; lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|tx_out[0]~in0 ; lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rx_outclock ; lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|pll~ENAOUT1 ; 9.432 ns                    ; 8.853 ns                  ; 1.544 ns                ;
; 7.309 ns ; None                 ; lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[6]  ; lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|tx_out[0]~in6 ; lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rx_outclock ; lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|pll~ENAOUT1 ; 9.432 ns                    ; 8.853 ns                  ; 1.544 ns                ;
; 7.310 ns ; None                 ; lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[9]  ; lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|tx_out[1]~in1 ; lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rx_outclock ; lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|pll~ENAOUT1 ; 9.432 ns                    ; 8.855 ns                  ; 1.545 ns                ;
; 7.310 ns ; None                 ; lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[11] ; lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|tx_out[1]~in3 ; lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rx_outclock ; lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|pll~ENAOUT1 ; 9.432 ns                    ; 8.855 ns                  ; 1.545 ns                ;
; 7.310 ns ; None                 ; lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[1]  ; lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|tx_out[0]~in1 ; lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rx_outclock ; lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|pll~ENAOUT1 ; 9.432 ns                    ; 8.853 ns                  ; 1.543 ns                ;
; 7.311 ns ; None                 ; lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[15] ; lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|tx_out[1]~in7 ; lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rx_outclock ; lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|pll~ENAOUT1 ; 9.432 ns                    ; 8.855 ns                  ; 1.544 ns                ;
; 7.312 ns ; None                 ; lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[8]  ; lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|tx_out[1]~in0 ; lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rx_outclock ; lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|pll~ENAOUT1 ; 9.432 ns                    ; 8.855 ns                  ; 1.543 ns                ;
+----------+----------------------+----------------------------------------------------------------+--------------------------------------------------------------------+------------------------------------------------------------------+------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rx_outclock'                                                                                                                                                                                                                                                                                                                                                                                                                                                               ;
+-----------------------------------------+-----------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------+------------------------------------------------------------------+------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                                                                            ; To                                                                                                ; From Clock                                                       ; To Clock                                                         ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------+------------------------------------------------------------------+------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+
; 5.994 ns                                ; 283.37 MHz ( period = 3.529 ns )                    ; mult:mult_inst|altmult_add:ALTMULT_ADD_component|mult_add_v4n1:auto_generated|mac_mult1~DATAOUT15               ; lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[14]                                    ; lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rx_outclock ; lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rx_outclock ; 9.523 ns                    ; 8.900 ns                  ; 2.906 ns                ;
; 5.994 ns                                ; 283.37 MHz ( period = 3.529 ns )                    ; mult:mult_inst|altmult_add:ALTMULT_ADD_component|mult_add_v4n1:auto_generated|mac_mult1~DATAOUT14               ; lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[14]                                    ; lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rx_outclock ; lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rx_outclock ; 9.523 ns                    ; 8.900 ns                  ; 2.906 ns                ;