diff_io_top.tan.qmsg

Altera FPGA CPLD设计高级篇电子书籍

{ "Info" "ITAN_NO_REG2REG_EXIST" "lvds_rx:lvds_rx_inst\|altlvds_rx:altlvds_rx_component\|pll " "Info: No valid register-to-register paths exist for clock lvds_rx:lvds_rx_inst\|altlvds_rx:altlvds_rx_component\|pll" {  } {  } 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "lvds_rx:lvds_rx_inst\|altlvds_rx:altlvds_rx_component\|rx_outclock register mult:mult_inst\|altmult_add:ALTMULT_ADD_component\|mult_add_v4n1:auto_generated\|mac_mult1~DATAOUT15 register lvds_tx:lvds_tx_inst\|altlvds_tx:altlvds_tx_component\|txreg\[14\] 5.994 ns " "Info: Slack time is 5.994 ns for clock lvds_rx:lvds_rx_inst\|altlvds_rx:altlvds_rx_component\|rx_outclock between source register mult:mult_inst\|altmult_add:ALTMULT_ADD_component\|mult_add_v4n1:auto_generated\|mac_mult1~DATAOUT15 and destination register lvds_tx:lvds_tx_inst\|altlvds_tx:altlvds_tx_component\|txreg\[14\]" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "283.37 MHz 3.529 ns " "Info: Fmax is 283.37 MHz (period= 3.529 ns)" {  } {  } 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "8.900 ns + Largest register register " "Info: + Largest register to register requirement is 8.900 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "9.523 ns + " "Info: + Setup relationship between source and destination is 9.523 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 9.614 ns " "Info: + Latch edge is 9.614 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination lvds_rx:lvds_rx_inst\|altlvds_rx:altlvds_rx_component\|rx_outclock 9.523 ns 0.091 ns  50 " "Info: Clock period of Destination clock lvds_rx:lvds_rx_inst\|altlvds_rx:altlvds_rx_component\|rx_outclock is 9.523 ns with  offset of 0.091 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0}  } {  } 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.091 ns " "Info: - Launch edge is 0.091 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source lvds_rx:lvds_rx_inst\|altlvds_rx:altlvds_rx_component\|rx_outclock 9.523 ns 0.091 ns  50 " "Info: Clock period of Source clock lvds_rx:lvds_rx_inst\|altlvds_rx:altlvds_rx_component\|rx_outclock is 9.523 ns with  offset of 0.091 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0}  } {  } 0}  } {  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.455 ns + Largest " "Info: + Largest clock skew is -0.455 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "lvds_rx:lvds_rx_inst\|altlvds_rx:altlvds_rx_component\|rx_outclock destination 1.902 ns + Shortest register " "Info: + Shortest clock path from clock lvds_rx:lvds_rx_inst\|altlvds_rx:altlvds_rx_component\|rx_outclock to destination register is 1.902 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lvds_rx:lvds_rx_inst\|altlvds_rx:altlvds_rx_component\|rx_outclock 1 CLK PLL_1 68 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 68; CLK Node = 'lvds_rx:lvds_rx_inst\|altlvds_rx:altlvds_rx_component\|rx_outclock'" {  } { { "E:/examples/Examples-10-2/Verilog/db/Diff_io_top_cmp.qrpt" "" "" { Report "E:/examples/Examples-10-2/Verilog/db/Diff_io_top_cmp.qrpt" Compiler "Diff_io_top" "UNKNOWN" "V1" "E:/examples/Examples-10-2/Verilog/db/Diff_io_top.quartus_db" { Floorplan "" "" "" { lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rx_outclock } "NODE_NAME" } } } { "d:/altera/quartus41/libraries/megafunctions/altlvds_rx.tdf" "" "" { Text "d:/altera/quartus41/libraries/megafunctions/altlvds_rx.tdf" 972 6 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.342 ns) + CELL(0.560 ns) 1.902 ns lvds_tx:lvds_tx_inst\|altlvds_tx:altlvds_tx_component\|txreg\[14\] 2 REG LC_X3_Y28_N4 1 " "Info: 2: + IC(1.342 ns) + CELL(0.560 ns) = 1.902 ns; Loc. = LC_X3_Y28_N4; Fanout = 1; REG Node = 'lvds_tx:lvds_tx_inst\|altlvds_tx:altlvds_tx_component\|txreg\[14\]'" {  } { { "E:/examples/Examples-10-2/Verilog/db/Diff_io_top_cmp.qrpt" "" "" { Report "E:/examples/Examples-10-2/Verilog/db/Diff_io_top_cmp.qrpt" Compiler "Diff_io_top" "UNKNOWN" "V1" "E:/examples/Examples-10-2/Verilog/db/Diff_io_top.quartus_db" { Floorplan "" "" "1.902 ns" { lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rx_outclock lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[14] } "NODE_NAME" } } } { "d:/altera/quartus41/libraries/megafunctions/altlvds_tx.tdf" "" "" { Text "d:/altera/quartus41/libraries/megafunctions/altlvds_tx.tdf" 418 10 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.560 ns 29.44 % " "Info: Total cell delay = 0.560 ns ( 29.44 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.342 ns 70.56 % " "Info: Total interconnect delay = 1.342 ns ( 70.56 % )" {  } {  } 0}  } { { "E:/examples/Examples-10-2/Verilog/db/Diff_io_top_cmp.qrpt" "" "" { Report "E:/examples/Examples-10-2/Verilog/db/Diff_io_top_cmp.qrpt" Compiler "Diff_io_top" "UNKNOWN" "V1" "E:/examples/Examples-10-2/Verilog/db/Diff_io_top.quartus_db" { Floorplan "" "" "1.902 ns" { lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rx_outclock lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[14] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "lvds_rx:lvds_rx_inst\|altlvds_rx:altlvds_rx_component\|rx_outclock source 2.357 ns - Longest register " "Info: - Longest clock path from clock lvds_rx:lvds_rx_inst\|altlvds_rx:altlvds_rx_component\|rx_outclock to source register is 2.357 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lvds_rx:lvds_rx_inst\|altlvds_rx:altlvds_rx_component\|rx_outclock 1 CLK PLL_1 68 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 68; CLK Node = 'lvds_rx:lvds_rx_inst\|altlvds_rx:altlvds_rx_component\|rx_outclock'" {  } { { "E:/examples/Examples-10-2/Verilog/db/Diff_io_top_cmp.qrpt" "" "" { Report "E:/examples/Examples-10-2/Verilog/db/Diff_io_top_cmp.qrpt" Compiler "Diff_io_top" "UNKNOWN" "V1" "E:/examples/Examples-10-2/Verilog/db/Diff_io_top.quartus_db" { Floorplan "" "" "" { lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rx_outclock } "NODE_NAME" } } } { "d:/altera/quartus41/libraries/megafunctions/altlvds_rx.tdf" "" "" { Text "d:/altera/quartus41/libraries/megafunctions/altlvds_rx.tdf" 972 6 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.342 ns) + CELL(1.015 ns) 2.357 ns mult:mult_inst\|altmult_add:ALTMULT_ADD_component\|mult_add_v4n1:auto_generated\|mac_mult1~DATAOUT15 2 REG DSPMULT_X10_Y29_N0 16 " "Info: 2: + IC(1.342 ns) + CELL(1.015 ns) = 2.357 ns; Loc. = DSPMULT_X10_Y29_N0; Fanout = 16; REG Node = 'mult:mult_inst\|altmult_add:ALTMULT_ADD_component\|mult_add_v4n1:auto_generated\|mac_mult1~DATAOUT15'" {  } { { "E:/examples/Examples-10-2/Verilog/db/Diff_io_top_cmp.qrpt" "" "" { Report "E:/examples/Examples-10-2/Verilog/db/Diff_io_top_cmp.qrpt" Compiler "Diff_io_top" "UNKNOWN" "V1" "E:/examples/Examples-10-2/Verilog/db/Diff_io_top.quartus_db" { Floorplan "" "" "2.357 ns" { lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rx_outclock mult:mult_inst|altmult_add:ALTMULT_ADD_component|mult_add_v4n1:auto_generated|mac_mult1~DATAOUT15 } "NODE_NAME" } } } { "E:/examples/Examples-10-2/Verilog/db/mult_add_v4n1.tdf" "" "" { Text "E:/examples/Examples-10-2/Verilog/db/mult_add_v4n1.tdf" 42 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.015 ns 43.06 % " "Info: Total cell delay = 1.015 ns ( 43.06 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.342 ns 56.94 % " "Info: Total interconnect delay = 1.342 ns ( 56.94 % )" {  } {  } 0}  } { { "E:/examples/Examples-10-2/Verilog/db/Diff_io_top_cmp.qrpt" "" "" { Report "E:/examples/Examples-10-2/Verilog/db/Diff_io_top_cmp.qrpt" Compiler "Diff_io_top" "UNKNOWN" "V1" "E:/examples/Examples-10-2/Verilog/db/Diff_io_top.quartus_db" { Floorplan "" "" "2.357 ns" { lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rx_outclock mult:mult_inst|altmult_add:ALTMULT_ADD_component|mult_add_v4n1:auto_generated|mac_mult1~DATAOUT15 } "NODE_NAME" } } }  } 0}  } { { "E:/examples/Examples-10-2/Verilog/db/Diff_io_top_cmp.qrpt" "" "" { Report "E:/examples/Examples-10-2/Verilog/db/Diff_io_top_cmp.qrpt" Compiler "Diff_io_top" "UNKNOWN" "V1" "E:/examples/Examples-10-2/Verilog/db/Diff_io_top.quartus_db" { Floorplan "" "" "1.902 ns" { lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rx_outclock lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[14] } "NODE_NAME" } } } { "E:/examples/Examples-10-2/Verilog/db/Diff_io_top_cmp.qrpt" "" "" { Report "E:/examples/Examples-10-2/Verilog/db/Diff_io_top_cmp.qrpt" Compiler "Diff_io_top" "UNKNOWN" "V1" "E:/examples/Examples-10-2/Verilog/db/Diff_io_top.quartus_db" { Floorplan "" "" "2.357 ns" { lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rx_outclock mult:mult_inst|altmult_add:ALTMULT_ADD_component|mult_add_v4n1:auto_generated|mac_mult1~DATAOUT15 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.158 ns - " "Info: - Micro clock to output delay of source is 0.158 ns" {  } { { "E:/examples/Examples-10-2/Verilog/db/mult_add_v4n1.tdf" "" "" { Text "E:/examples/Examples-10-2/Verilog/db/mult_add_v4n1.tdf" 42 2 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns - " "Info: - Micro setup delay of destination is 0.010 ns" {  } { { "d:/altera/quartus41/libraries/megafunctions/altlvds_tx.tdf" "" "" { Text "d:/altera/quartus41/libraries/megafunctions/altlvds_tx.tdf" 418 10 0 } }  } 0}  } { { "E:/examples/Examples-10-2/Verilog/db/Diff_io_top_cmp.qrpt" "" "" { Report "E:/examples/Examples-10-2/Verilog/db/Diff_io_top_cmp.qrpt" Compiler "Diff_io_top" "UNKNOWN" "V1" "E:/examples/Examples-10-2/Verilog/db/Diff_io_top.quartus_db" { Floorplan "" "" "1.902 ns" { lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rx_outclock lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[14] } "NODE_NAME" } } } { "E:/examples/Examples-10-2/Verilog/db/Diff_io_top_cmp.qrpt" "" "" { Report "E:/examples/Examples-10-2/Verilog/db/Diff_io_top_cmp.qrpt" Compiler "Diff_io_top" "UNKNOWN" "V1" "E:/examples/Examples-10-2/Verilog/db/Diff_io_top.quartus_db" { Floorplan "" "" "2.357 ns" { lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rx_outclock mult:mult_inst|altmult_add:ALTMULT_ADD_component|mult_add_v4n1:auto_generated|mac_mult1~DATAOUT15 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.906 ns - Longest register register " "Info: - Longest register to register delay is 2.906 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.161 ns) 0.161 ns mult:mult_inst\|altmult_add:ALTMULT_ADD_component\|mult_add_v4n1:auto_generated\|mac_mult1~DATAOUT15 1 REG DSPMULT_X10_Y29_N0 16 " "Info: 1: + IC(0.000 ns) + CELL(0.161 ns) = 0.161 ns; Loc. = DSPMULT_X10_Y29_N0; Fanout = 16; REG Node = 'mult:mult_inst\|altmult_add:ALTMULT_ADD_component\|mult_add_v4n1:auto_generated\|mac_mult1~DATAOUT15'" {  } { { "E:/examples/Examples-10-2/Verilog/db/Diff_io_top_cmp.qrpt" "" "" { Report "E:/examples/Examples-10-2/Verilog/db/Diff_io_top_cmp.qrpt" Compiler "Diff_io_top" "UNKNOWN" "V1" "E:/examples/Examples-10-2/Verilog/db/Diff_io_top.quartus_db" { Floorplan "" "" "" { mult:mult_inst|altmult_add:ALTMULT_ADD_component|mult_add_v4n1:auto_generated|mac_mult1~DATAOUT15 } "NODE_NAME" } } } { "E:/examples/Examples-10-2/Verilog/db/mult_add_v4n1.tdf" "" "" { Text "E:/examples/Examples-10-2/Verilog/db/mult_add_v4n1.tdf" 42 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.966 ns) 1.127 ns mult:mult_inst\|altmult_add:ALTMULT_ADD_component\|mult_add_v4n1:auto_generated\|result\[14\] 2 COMB DSPOUT_X11_Y23_N0 1 " "Info: 2: + IC(0.000 ns) + CELL(0.966 ns) = 1.127 ns; Loc. = DSPOUT_X11_Y23_N0; Fanout = 1; COMB Node = 'mult:mult_inst\|altmult_add:ALTMULT_ADD_component\|mult_add_v4n1:auto_generated\|result\[14\]'" {  } { { "E:/examples/Examples-10-2/Verilog/db/Diff_io_top_cmp.qrpt" "" "" { Report "E:/examples/Examples-10-2/Verilog/db/Diff_io_top_cmp.qrpt" Compiler "Diff_io_top" "UNKNOWN" "V1" "E:/examples/Examples-10-2/Verilog/db/Diff_io_top.quartus_db" { Floorplan "" "" "0.966 ns" { mult:mult_inst|altmult_add:ALTMULT_ADD_component|mult_add_v4n1:auto_generated|mac_mult1~DATAOUT15 mult:mult_inst|altmult_add:ALTMULT_ADD_component|mult_add_v4n1:auto_generated|result[14] } "NODE_NAME" } } } { "E:/examples/Examples-10-2/Verilog/db/mult_add_v4n1.tdf" "" "" { Text "E:/examples/Examples-10-2/Verilog/db/mult_add_v4n1.tdf" 39 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.544 ns) + CELL(0.235 ns) 2.906 ns lvds_tx:lvds_tx_inst\|altlvds_tx:altlvds_tx_component\|txreg\[14\] 3 REG LC_X3_Y28_N4 1 " "Info: 3: + IC(1.544 ns) + CELL(0.235 ns) = 2.906 ns; Loc. = LC_X3_Y28_N4; Fanout = 1; REG Node = 'lvds_tx:lvds_tx_inst\|altlvds_tx:altlvds_tx_component\|txreg\[14\]'" {  } { { "E:/examples/Examples-10-2/Verilog/db/Diff_io_top_cmp.qrpt" "" "" { Report "E:/examples/Examples-10-2/Verilog/db/Diff_io_top_cmp.qrpt" Compiler "Diff_io_top" "UNKNOWN" "V1" "E:/examples/Examples-10-2/Verilog/db/Diff_io_top.quartus_db" { Floorplan "" "" "1.779 ns" { mult:mult_inst|altmult_add:ALTMULT_ADD_component|mult_add_v4n1:auto_generated|result[14] lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[14] } "NODE_NAME" } } } { "d:/altera/quartus41/libraries/megafunctions/altlvds_tx.tdf" "" "" { Text "d:/altera/quartus41/libraries/megafunctions/altlvds_tx.tdf" 418 10 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.362 ns 46.87 % " "Info: Total cell delay = 1.362 ns ( 46.87 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.544 ns 53.13 % " "Info: Total interconnect delay = 1.544 ns ( 53.13 % )" {  } {  } 0}  } { { "E:/examples/Examples-10-2/Verilog/db/Diff_io_top_cmp.qrpt" "" "" { Report "E:/examples/Examples-10-2/Verilog/db/Diff_io_top_cmp.qrpt" Compiler "Diff_io_top" "UNKNOWN" "V1" "E:/examples/Examples-10-2/Verilog/db/Diff_io_top.quartus_db" { Floorplan "" "" "2.906 ns" { mult:mult_inst|altmult_add:ALTMULT_ADD_component|mult_add_v4n1:auto_generated|mac_mult1~DATAOUT15 mult:mult_inst|altmult_add:ALTMULT_ADD_component|mult_add_v4n1:auto_generated|result[14] lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[14] } "NODE_NAME" } } }  } 0}  } { { "E:/examples/Examples-10-2/Verilog/db/Diff_io_top_cmp.qrpt" "" "" { Report "E:/examples/Examples-10-2/Verilog/db/Diff_io_top_cmp.qrpt" Compiler "Diff_io_top" "UNKNOWN" "V1" "E:/examples/Examples-10-2/Verilog/db/Diff_io_top.quartus_db" { Floorplan "" "" "1.902 ns" { lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rx_outclock lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[14] } "NODE_NAME" } } } { "E:/examples/Examples-10-2/Verilog/db/Diff_io_top_cmp.qrpt" "" "" { Report "E:/examples/Examples-10-2/Verilog/db/Diff_io_top_cmp.qrpt" Compiler "Diff_io_top" "UNKNOWN" "V1" "E:/examples/Examples-10-2/Verilog/db/Diff_io_top.quartus_db" { Floorplan "" "" "2.357 ns" { lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rx_outclock mult:mult_inst|altmult_add:ALTMULT_ADD_component|mult_add_v4n1:auto_generated|mac_mult1~DATAOUT15 } "NODE_NAME" } } } { "E:/examples/Examples-10-2/Verilog/db/Diff_io_top_cmp.qrpt" "" "" { Report "E:/examples/Examples-10-2/Verilog/db/Diff_io_top_cmp.qrpt" Compiler "Diff_io_top" "UNKNOWN" "V1" "E:/examples/Examples-10-2/Verilog/db/Diff_io_top.quartus_db" { Floorplan "" "" "2.906 ns" { mult:mult_inst|altmult_add:ALTMULT_ADD_component|mult_add_v4n1:auto_generated|mac_mult1~DATAOUT15 mult:mult_inst|altmult_add:ALTMULT_ADD_component|mult_add_v4n1:auto_generated|result[14] lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[14] } "NODE_NAME" } } }  } 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "rx_inclock " "Info: No valid register-to-register paths exist for clock rx_inclock" {  } {  } 0}
{ "Info" "ITAN_REQUIREMENTS_MET" "" "Info: All timing requirements were met. See Report window for more details." {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Sep 13 22:27:28 2004 " "Info: Processing ended: Mon Sep 13 22:27:28 2004" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0}  } {  } 0}