diff_io_top.tan.qmsg

Altera FPGA CPLD设计高级篇电子书籍

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 207 08/26/2004 Service Pack 1.04 SJ Full Version " "Info: Version 4.1 Build 207 08/26/2004 Service Pack 1.04 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Sep 13 22:27:27 2004 " "Info: Processing started: Mon Sep 13 22:27:27 2004" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --import_settings_files=off --export_settings_files=off Diff_io_top -c Diff_io_top --timing_analysis_only " "Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off Diff_io_top -c Diff_io_top --timing_analysis_only" {  } {  } 0}
{ "Info" "ITAN_SLACK_ANALYSIS" "" "Info: Found timing assignments -- calculating delays" {  } {  } 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "lvds_rx:lvds_rx_inst\|altlvds_rx:altlvds_rx_component\|pll~ENAOUT0 " "Info: No valid register-to-register paths exist for clock lvds_rx:lvds_rx_inst\|altlvds_rx:altlvds_rx_component\|pll~ENAOUT0" {  } {  } 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "lvds_rx:lvds_rx_inst\|altlvds_rx:altlvds_rx_component\|pll~ENAOUT1 register lvds_tx:lvds_tx_inst\|altlvds_tx:altlvds_tx_component\|txreg\[13\] register lvds_tx:lvds_tx_inst\|altlvds_tx:altlvds_tx_component\|tx_out\[1\]~in5 7.287 ns " "Info: Slack time is 7.287 ns for clock lvds_rx:lvds_rx_inst\|altlvds_rx:altlvds_rx_component\|pll~ENAOUT1 between source register lvds_tx:lvds_tx_inst\|altlvds_tx:altlvds_tx_component\|txreg\[13\] and destination register lvds_tx:lvds_tx_inst\|altlvds_tx:altlvds_tx_component\|tx_out\[1\]~in5" { { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "8.855 ns + Largest register register " "Info: + Largest register to register requirement is 8.855 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "9.432 ns + " "Info: + Setup relationship between source and destination is 9.432 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 9.523 ns " "Info: + Latch edge is 9.523 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination lvds_rx:lvds_rx_inst\|altlvds_rx:altlvds_rx_component\|pll~ENAOUT1 9.523 ns 0.000 ns  50 " "Info: Clock period of Destination clock lvds_rx:lvds_rx_inst\|altlvds_rx:altlvds_rx_component\|pll~ENAOUT1 is 9.523 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0}  } {  } 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.091 ns " "Info: - Launch edge is 0.091 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source lvds_rx:lvds_rx_inst\|altlvds_rx:altlvds_rx_component\|rx_outclock 9.523 ns 0.091 ns  50 " "Info: Clock period of Source clock lvds_rx:lvds_rx_inst\|altlvds_rx:altlvds_rx_component\|rx_outclock is 9.523 ns with  offset of 0.091 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0}  } {  } 0}  } {  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.321 ns + Largest " "Info: + Largest clock skew is -0.321 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "lvds_rx:lvds_rx_inst\|altlvds_rx:altlvds_rx_component\|pll~ENAOUT1 destination 1.581 ns + Shortest register " "Info: + Shortest clock path from clock lvds_rx:lvds_rx_inst\|altlvds_rx:altlvds_rx_component\|pll~ENAOUT1 to destination register is 1.581 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lvds_rx:lvds_rx_inst\|altlvds_rx:altlvds_rx_component\|pll~ENAOUT1 1 CLK PLL_1 24 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 24; CLK Node = 'lvds_rx:lvds_rx_inst\|altlvds_rx:altlvds_rx_component\|pll~ENAOUT1'" {  } { { "E:/examples/Examples-10-2/Verilog/db/Diff_io_top_cmp.qrpt" "" "" { Report "E:/examples/Examples-10-2/Verilog/db/Diff_io_top_cmp.qrpt" Compiler "Diff_io_top" "UNKNOWN" "V1" "E:/examples/Examples-10-2/Verilog/db/Diff_io_top.quartus_db" { Floorplan "" "" "" { lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|pll~ENAOUT1 } "NODE_NAME" } } } { "d:/altera/quartus41/libraries/megafunctions/altlvds_rx.tdf" "" "" { Text "d:/altera/quartus41/libraries/megafunctions/altlvds_rx.tdf" 402 7 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.654 ns) + CELL(0.927 ns) 1.581 ns lvds_tx:lvds_tx_inst\|altlvds_tx:altlvds_tx_component\|tx_out\[1\]~in5 2 REG SERDESTX_X0_Y28_N5 0 " "Info: 2: + IC(0.654 ns) + CELL(0.927 ns) = 1.581 ns; Loc. = SERDESTX_X0_Y28_N5; Fanout = 0; REG Node = 'lvds_tx:lvds_tx_inst\|altlvds_tx:altlvds_tx_component\|tx_out\[1\]~in5'" {  } { { "E:/examples/Examples-10-2/Verilog/db/Diff_io_top_cmp.qrpt" "" "" { Report "E:/examples/Examples-10-2/Verilog/db/Diff_io_top_cmp.qrpt" Compiler "Diff_io_top" "UNKNOWN" "V1" "E:/examples/Examples-10-2/Verilog/db/Diff_io_top.quartus_db" { Floorplan "" "" "1.581 ns" { lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|pll~ENAOUT1 lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|tx_out[1]~in5 } "NODE_NAME" } } } { "d:/altera/quartus41/libraries/megafunctions/altlvds_tx.tdf" "" "" { Text "d:/altera/quartus41/libraries/megafunctions/altlvds_tx.tdf" 225 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.927 ns 58.63 % " "Info: Total cell delay = 0.927 ns ( 58.63 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.654 ns 41.37 % " "Info: Total interconnect delay = 0.654 ns ( 41.37 % )" {  } {  } 0}  } { { "E:/examples/Examples-10-2/Verilog/db/Diff_io_top_cmp.qrpt" "" "" { Report "E:/examples/Examples-10-2/Verilog/db/Diff_io_top_cmp.qrpt" Compiler "Diff_io_top" "UNKNOWN" "V1" "E:/examples/Examples-10-2/Verilog/db/Diff_io_top.quartus_db" { Floorplan "" "" "1.581 ns" { lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|pll~ENAOUT1 lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|tx_out[1]~in5 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "lvds_rx:lvds_rx_inst\|altlvds_rx:altlvds_rx_component\|rx_outclock source 1.902 ns - Longest register " "Info: - Longest clock path from clock lvds_rx:lvds_rx_inst\|altlvds_rx:altlvds_rx_component\|rx_outclock to source register is 1.902 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lvds_rx:lvds_rx_inst\|altlvds_rx:altlvds_rx_component\|rx_outclock 1 CLK PLL_1 68 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 68; CLK Node = 'lvds_rx:lvds_rx_inst\|altlvds_rx:altlvds_rx_component\|rx_outclock'" {  } { { "E:/examples/Examples-10-2/Verilog/db/Diff_io_top_cmp.qrpt" "" "" { Report "E:/examples/Examples-10-2/Verilog/db/Diff_io_top_cmp.qrpt" Compiler "Diff_io_top" "UNKNOWN" "V1" "E:/examples/Examples-10-2/Verilog/db/Diff_io_top.quartus_db" { Floorplan "" "" "" { lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rx_outclock } "NODE_NAME" } } } { "d:/altera/quartus41/libraries/megafunctions/altlvds_rx.tdf" "" "" { Text "d:/altera/quartus41/libraries/megafunctions/altlvds_rx.tdf" 972 6 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.342 ns) + CELL(0.560 ns) 1.902 ns lvds_tx:lvds_tx_inst\|altlvds_tx:altlvds_tx_component\|txreg\[13\] 2 REG LC_X3_Y28_N8 1 " "Info: 2: + IC(1.342 ns) + CELL(0.560 ns) = 1.902 ns; Loc. = LC_X3_Y28_N8; Fanout = 1; REG Node = 'lvds_tx:lvds_tx_inst\|altlvds_tx:altlvds_tx_component\|txreg\[13\]'" {  } { { "E:/examples/Examples-10-2/Verilog/db/Diff_io_top_cmp.qrpt" "" "" { Report "E:/examples/Examples-10-2/Verilog/db/Diff_io_top_cmp.qrpt" Compiler "Diff_io_top" "UNKNOWN" "V1" "E:/examples/Examples-10-2/Verilog/db/Diff_io_top.quartus_db" { Floorplan "" "" "1.902 ns" { lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rx_outclock lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[13] } "NODE_NAME" } } } { "d:/altera/quartus41/libraries/megafunctions/altlvds_tx.tdf" "" "" { Text "d:/altera/quartus41/libraries/megafunctions/altlvds_tx.tdf" 418 10 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.560 ns 29.44 % " "Info: Total cell delay = 0.560 ns ( 29.44 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.342 ns 70.56 % " "Info: Total interconnect delay = 1.342 ns ( 70.56 % )" {  } {  } 0}  } { { "E:/examples/Examples-10-2/Verilog/db/Diff_io_top_cmp.qrpt" "" "" { Report "E:/examples/Examples-10-2/Verilog/db/Diff_io_top_cmp.qrpt" Compiler "Diff_io_top" "UNKNOWN" "V1" "E:/examples/Examples-10-2/Verilog/db/Diff_io_top.quartus_db" { Floorplan "" "" "1.902 ns" { lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rx_outclock lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[13] } "NODE_NAME" } } }  } 0}  } { { "E:/examples/Examples-10-2/Verilog/db/Diff_io_top_cmp.qrpt" "" "" { Report "E:/examples/Examples-10-2/Verilog/db/Diff_io_top_cmp.qrpt" Compiler "Diff_io_top" "UNKNOWN" "V1" "E:/examples/Examples-10-2/Verilog/db/Diff_io_top.quartus_db" { Floorplan "" "" "1.581 ns" { lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|pll~ENAOUT1 lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|tx_out[1]~in5 } "NODE_NAME" } } } { "E:/examples/Examples-10-2/Verilog/db/Diff_io_top_cmp.qrpt" "" "" { Report "E:/examples/Examples-10-2/Verilog/db/Diff_io_top_cmp.qrpt" Compiler "Diff_io_top" "UNKNOWN" "V1" "E:/examples/Examples-10-2/Verilog/db/Diff_io_top.quartus_db" { Floorplan "" "" "1.902 ns" { lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rx_outclock lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[13] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.176 ns - " "Info: - Micro clock to output delay of source is 0.176 ns" {  } { { "d:/altera/quartus41/libraries/megafunctions/altlvds_tx.tdf" "" "" { Text "d:/altera/quartus41/libraries/megafunctions/altlvds_tx.tdf" 418 10 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.080 ns - " "Info: - Micro setup delay of destination is 0.080 ns" {  } { { "d:/altera/quartus41/libraries/megafunctions/altlvds_tx.tdf" "" "" { Text "d:/altera/quartus41/libraries/megafunctions/altlvds_tx.tdf" 225 2 0 } }  } 0}  } { { "E:/examples/Examples-10-2/Verilog/db/Diff_io_top_cmp.qrpt" "" "" { Report "E:/examples/Examples-10-2/Verilog/db/Diff_io_top_cmp.qrpt" Compiler "Diff_io_top" "UNKNOWN" "V1" "E:/examples/Examples-10-2/Verilog/db/Diff_io_top.quartus_db" { Floorplan "" "" "1.581 ns" { lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|pll~ENAOUT1 lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|tx_out[1]~in5 } "NODE_NAME" } } } { "E:/examples/Examples-10-2/Verilog/db/Diff_io_top_cmp.qrpt" "" "" { Report "E:/examples/Examples-10-2/Verilog/db/Diff_io_top_cmp.qrpt" Compiler "Diff_io_top" "UNKNOWN" "V1" "E:/examples/Examples-10-2/Verilog/db/Diff_io_top.quartus_db" { Floorplan "" "" "1.902 ns" { lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rx_outclock lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[13] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.568 ns - Longest register register " "Info: - Longest register to register delay is 1.568 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lvds_tx:lvds_tx_inst\|altlvds_tx:altlvds_tx_component\|txreg\[13\] 1 REG LC_X3_Y28_N8 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X3_Y28_N8; Fanout = 1; REG Node = 'lvds_tx:lvds_tx_inst\|altlvds_tx:altlvds_tx_component\|txreg\[13\]'" {  } { { "E:/examples/Examples-10-2/Verilog/db/Diff_io_top_cmp.qrpt" "" "" { Report "E:/examples/Examples-10-2/Verilog/db/Diff_io_top_cmp.qrpt" Compiler "Diff_io_top" "UNKNOWN" "V1" "E:/examples/Examples-10-2/Verilog/db/Diff_io_top.quartus_db" { Floorplan "" "" "" { lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[13] } "NODE_NAME" } } } { "d:/altera/quartus41/libraries/megafunctions/altlvds_tx.tdf" "" "" { Text "d:/altera/quartus41/libraries/megafunctions/altlvds_tx.tdf" 418 10 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.144 ns) + CELL(0.424 ns) 1.568 ns lvds_tx:lvds_tx_inst\|altlvds_tx:altlvds_tx_component\|tx_out\[1\]~in5 2 REG SERDESTX_X0_Y28_N5 0 " "Info: 2: + IC(1.144 ns) + CELL(0.424 ns) = 1.568 ns; Loc. = SERDESTX_X0_Y28_N5; Fanout = 0; REG Node = 'lvds_tx:lvds_tx_inst\|altlvds_tx:altlvds_tx_component\|tx_out\[1\]~in5'" {  } { { "E:/examples/Examples-10-2/Verilog/db/Diff_io_top_cmp.qrpt" "" "" { Report "E:/examples/Examples-10-2/Verilog/db/Diff_io_top_cmp.qrpt" Compiler "Diff_io_top" "UNKNOWN" "V1" "E:/examples/Examples-10-2/Verilog/db/Diff_io_top.quartus_db" { Floorplan "" "" "1.568 ns" { lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[13] lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|tx_out[1]~in5 } "NODE_NAME" } } } { "d:/altera/quartus41/libraries/megafunctions/altlvds_tx.tdf" "" "" { Text "d:/altera/quartus41/libraries/megafunctions/altlvds_tx.tdf" 225 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.424 ns 27.04 % " "Info: Total cell delay = 0.424 ns ( 27.04 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.144 ns 72.96 % " "Info: Total interconnect delay = 1.144 ns ( 72.96 % )" {  } {  } 0}  } { { "E:/examples/Examples-10-2/Verilog/db/Diff_io_top_cmp.qrpt" "" "" { Report "E:/examples/Examples-10-2/Verilog/db/Diff_io_top_cmp.qrpt" Compiler "Diff_io_top" "UNKNOWN" "V1" "E:/examples/Examples-10-2/Verilog/db/Diff_io_top.quartus_db" { Floorplan "" "" "1.568 ns" { lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[13] lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|tx_out[1]~in5 } "NODE_NAME" } } }  } 0}  } { { "E:/examples/Examples-10-2/Verilog/db/Diff_io_top_cmp.qrpt" "" "" { Report "E:/examples/Examples-10-2/Verilog/db/Diff_io_top_cmp.qrpt" Compiler "Diff_io_top" "UNKNOWN" "V1" "E:/examples/Examples-10-2/Verilog/db/Diff_io_top.quartus_db" { Floorplan "" "" "1.581 ns" { lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|pll~ENAOUT1 lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|tx_out[1]~in5 } "NODE_NAME" } } } { "E:/examples/Examples-10-2/Verilog/db/Diff_io_top_cmp.qrpt" "" "" { Report "E:/examples/Examples-10-2/Verilog/db/Diff_io_top_cmp.qrpt" Compiler "Diff_io_top" "UNKNOWN" "V1" "E:/examples/Examples-10-2/Verilog/db/Diff_io_top.quartus_db" { Floorplan "" "" "1.902 ns" { lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rx_outclock lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[13] } "NODE_NAME" } } } { "E:/examples/Examples-10-2/Verilog/db/Diff_io_top_cmp.qrpt" "" "" { Report "E:/examples/Examples-10-2/Verilog/db/Diff_io_top_cmp.qrpt" Compiler "Diff_io_top" "UNKNOWN" "V1" "E:/examples/Examples-10-2/Verilog/db/Diff_io_top.quartus_db" { Floorplan "" "" "1.568 ns" { lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[13] lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|tx_out[1]~in5 } "NODE_NAME" } } }  } 0}