mult_add_v4n1.tdf

Altera FPGA CPLD设计高级篇电子书籍

--altmult_add ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1="CLOCK0" ADDNSUB_MULTIPLIER_REGISTER1="CLOCK0" DEVICE_FAMILY="Stratix" DSP_BLOCK_BALANCING="Auto" INPUT_REGISTER_A0="CLOCK0" INPUT_REGISTER_B0="CLOCK0" INPUT_SOURCE_A0="DATAA" INPUT_SOURCE_B0="DATAB" MULTIPLIER1_DIRECTION="ADD" MULTIPLIER_REGISTER0="CLOCK0" NUMBER_OF_MULTIPLIERS=1 OUTPUT_REGISTER="UNREGISTERED" SIGNED_PIPELINE_REGISTER_A="CLOCK0" SIGNED_PIPELINE_REGISTER_B="CLOCK0" SIGNED_REGISTER_A="CLOCK0" SIGNED_REGISTER_B="CLOCK0" WIDTH_A=8 WIDTH_B=8 WIDTH_RESULT=16 clock0 dataa datab result CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=70
--VERSION_BEGIN 4.1 cbx_alt_ded_mult_y 2004:06:23:18:12:36:SJ cbx_altmult_add 2004:06:23:18:09:24:SJ cbx_cycloneii 2004:05:18:11:27:16:SJ cbx_lpm_add_sub 2004:06:23:12:24:04:SJ cbx_mgl 2004:06:17:17:30:06:SJ cbx_padd 2004:06:16:20:36:44:SJ cbx_parallel_add 2003:11:11:15:26:08:SJ cbx_stratix 2004:04:28:15:20:14:SJ cbx_stratixii 2004:05:18:11:28:28:SJ cbx_util 2004:03:29:17:03:30:SJ  VERSION_END


--  Copyright (C) 1988-2002 Altera Corporation
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--  to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
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FUNCTION stratix_mac_mult (aclr[3..0], clk[3..0], dataa[17..0], datab[17..0], ena[3..0], signa, signb)
WITH ( 	dataa_clear,	dataa_clock,	dataa_width,	datab_clear,	datab_clock,	datab_width,	output_clear,	output_clock,	signa_clear,	signa_clock,	signa_internally_grounded,	signb_clear,	signb_clock,	signb_internally_grounded) 
RETURNS ( dataout[35..0], scanouta[17..0], scanoutb[17..0]);
FUNCTION stratix_mac_out (aclr[3..0], addnsub0, addnsub1, clk[3..0], dataa[35..0], datab[35..0], datac[35..0], datad[35..0], ena[3..0], signa, signb, zeroacc)
WITH ( 	addnsub0_clear,	addnsub0_clock,	addnsub0_pipeline_clear,	addnsub0_pipeline_clock,	addnsub1_clear,	addnsub1_clock,	addnsub1_pipeline_clear,	addnsub1_pipeline_clock,	dataa_width,	datab_width,	datac_width,	datad_width,	dataout_width,	operation_mode,	output_clear,	output_clock,	signa_clear,	signa_clock,	signa_pipeline_clear,	signa_pipeline_clock,	signb_clear,	signb_clock,	signb_pipeline_clear,	signb_pipeline_clock,	zeroacc_clear,	zeroacc_clock,	zeroacc_pipeline_clear,	zeroacc_pipeline_clock) 
RETURNS ( accoverflow, dataout[dataout_width-1..0]);

--synthesis_resources = dsp_9bit 1 
SUBDESIGN mult_add_v4n1
( 
	clock0	:	input;
	dataa[7..0]	:	input;
	datab[7..0]	:	input;
	result[15..0]	:	output;
) 
VARIABLE 
	mac_mult1 : stratix_mac_mult
		WITH (
			dataa_clear = "3",
			dataa_clock = "0",
			dataa_width = 8,
			datab_clear = "3",
			datab_clock = "0",
			datab_width = 8,
			output_clear = "3",
			output_clock = "0"
		);
	mac_out2 : stratix_mac_out
		WITH (
			dataa_width = 16,
			dataout_width = 72,
			operation_mode = "output_only"
		);
	aclr0	: NODE;
	aclr1	: NODE;
	aclr2	: NODE;
	aclr3	: NODE;
	clock1	: NODE;
	clock2	: NODE;
	clock3	: NODE;
	dataa_bus[7..0]	: WIRE;
	datab_bus[7..0]	: WIRE;
	ena0	: NODE;
	ena1	: NODE;
	ena2	: NODE;
	ena3	: NODE;

BEGIN 
	mac_mult1.aclr[] = ( aclr3, aclr2, aclr1, aclr0);
	mac_mult1.clk[] = ( clock3, clock2, clock1, clock0);
	mac_mult1.dataa[] = ( B"1111111111", dataa_bus[7..0]);
	mac_mult1.datab[] = ( B"1111111111", datab_bus[7..0]);
	mac_mult1.ena[] = ( ena3, ena2, ena1, ena0);
	mac_mult1.signa = B"0";
	mac_mult1.signb = B"0";
	mac_out2.aclr[] = ( aclr3, aclr2, aclr1, aclr0);
	mac_out2.clk[] = ( clock3, clock2, clock1, clock0);
	mac_out2.dataa[] = ( B"00000000000000000000", mac_mult1.dataout[15..0]);
	mac_out2.ena[] = ( ena3, ena2, ena1, ena0);
	mac_out2.signa = B"0";
	mac_out2.signb = B"0";
	aclr0 = GND;
	aclr1 = GND;
	aclr2 = GND;
	aclr3 = GND;
	clock1 = VCC;
	clock2 = VCC;
	clock3 = VCC;
	dataa_bus[] = ( dataa[7..0]);
	datab_bus[] = ( datab[7..0]);
	ena0 = VCC;
	ena1 = VCC;
	ena2 = VCC;
	ena3 = VCC;
	result[15..0] = mac_out2.dataout[15..0];
END;
--VALID FILE