diff_io_top.hier_info

Altera FPGA CPLD设计高级篇电子书籍

|Diff_io_top
rx_in[0] => rx_in[0]~1.IN1
rx_in[1] => rx_in[1]~0.IN1
rx_inclock => rx_inclock~0.IN1
rx_data_align => rx_data_align~0.IN1
rx_locked <= lvds_rx:lvds_rx_inst.rx_locked
tx_out[0] <= lvds_tx:lvds_tx_inst.tx_out
tx_out[1] <= lvds_tx:lvds_tx_inst.tx_out
tx_outclock <= lvds_tx:lvds_tx_inst.tx_outclock


|Diff_io_top|lvds_rx:lvds_rx_inst
rx_in[0] => rx_in[0]~1.IN1
rx_in[1] => rx_in[1]~0.IN1
rx_inclock => rx_inclock~0.IN1
rx_data_align => rx_data_align~0.IN1
rx_out[0] <= altlvds_rx:altlvds_rx_component.rx_out
rx_out[1] <= altlvds_rx:altlvds_rx_component.rx_out
rx_out[2] <= altlvds_rx:altlvds_rx_component.rx_out
rx_out[3] <= altlvds_rx:altlvds_rx_component.rx_out
rx_out[4] <= altlvds_rx:altlvds_rx_component.rx_out
rx_out[5] <= altlvds_rx:altlvds_rx_component.rx_out
rx_out[6] <= altlvds_rx:altlvds_rx_component.rx_out
rx_out[7] <= altlvds_rx:altlvds_rx_component.rx_out
rx_out[8] <= altlvds_rx:altlvds_rx_component.rx_out
rx_out[9] <= altlvds_rx:altlvds_rx_component.rx_out
rx_out[10] <= altlvds_rx:altlvds_rx_component.rx_out
rx_out[11] <= altlvds_rx:altlvds_rx_component.rx_out
rx_out[12] <= altlvds_rx:altlvds_rx_component.rx_out
rx_out[13] <= altlvds_rx:altlvds_rx_component.rx_out
rx_out[14] <= altlvds_rx:altlvds_rx_component.rx_out
rx_out[15] <= altlvds_rx:altlvds_rx_component.rx_out
rx_locked <= altlvds_rx:altlvds_rx_component.rx_locked
rx_outclock <= altlvds_rx:altlvds_rx_component.rx_outclock


|Diff_io_top|lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component
rx_in[0] => rx[0].DATAIN
rx_in[1] => rx[1].DATAIN
rx_inclock => pll.CLK
rx_enable => ~NO_FANOUT~
rx_deskew => ~NO_FANOUT~
rx_pll_enable => ~NO_FANOUT~
rx_data_align => pll.COMPARATOR
rx_reset[0] => ~NO_FANOUT~
rx_reset[1] => ~NO_FANOUT~
rx_dpll_reset[0] => ~NO_FANOUT~
rx_dpll_reset[1] => ~NO_FANOUT~
rx_dpll_hold[0] => ~NO_FANOUT~
rx_dpll_hold[1] => ~NO_FANOUT~
rx_dpll_enable[0] => ~NO_FANOUT~
rx_dpll_enable[1] => ~NO_FANOUT~
rx_fifo_reset[0] => ~NO_FANOUT~
rx_fifo_reset[1] => ~NO_FANOUT~
rx_channel_data_align[0] => ~NO_FANOUT~
rx_channel_data_align[1] => ~NO_FANOUT~
rx_cda_reset[0] => ~NO_FANOUT~
rx_cda_reset[1] => ~NO_FANOUT~
rx_coreclk[0] => ~NO_FANOUT~
rx_coreclk[1] => ~NO_FANOUT~
pll_areset => ~NO_FANOUT~
rx_out[0] <= rxreg[0].DB_MAX_OUTPUT_PORT_TYPE
rx_out[1] <= rxreg[1].DB_MAX_OUTPUT_PORT_TYPE
rx_out[2] <= rxreg[2].DB_MAX_OUTPUT_PORT_TYPE
rx_out[3] <= rxreg[3].DB_MAX_OUTPUT_PORT_TYPE
rx_out[4] <= rxreg[4].DB_MAX_OUTPUT_PORT_TYPE
rx_out[5] <= rxreg[5].DB_MAX_OUTPUT_PORT_TYPE
rx_out[6] <= rxreg[6].DB_MAX_OUTPUT_PORT_TYPE
rx_out[7] <= rxreg[7].DB_MAX_OUTPUT_PORT_TYPE
rx_out[8] <= rxreg[8].DB_MAX_OUTPUT_PORT_TYPE
rx_out[9] <= rxreg[9].DB_MAX_OUTPUT_PORT_TYPE
rx_out[10] <= rxreg[10].DB_MAX_OUTPUT_PORT_TYPE
rx_out[11] <= rxreg[11].DB_MAX_OUTPUT_PORT_TYPE
rx_out[12] <= rxreg[12].DB_MAX_OUTPUT_PORT_TYPE
rx_out[13] <= rxreg[13].DB_MAX_OUTPUT_PORT_TYPE
rx_out[14] <= rxreg[14].DB_MAX_OUTPUT_PORT_TYPE
rx_out[15] <= rxreg[15].DB_MAX_OUTPUT_PORT_TYPE
rx_outclock <= pll.CLK2
rx_dpa_locked[0] <= <UNC>
rx_dpa_locked[1] <= <UNC>
rx_cda_max[0] <= <UNC>
rx_cda_max[1] <= <UNC>


|Diff_io_top|mult:mult_inst
clock0 => clock0~0.IN1
dataa_0[0] => dataa_0[0]~7.IN1
dataa_0[1] => dataa_0[1]~6.IN1
dataa_0[2] => dataa_0[2]~5.IN1
dataa_0[3] => dataa_0[3]~4.IN1
dataa_0[4] => dataa_0[4]~3.IN1
dataa_0[5] => dataa_0[5]~2.IN1
dataa_0[6] => dataa_0[6]~1.IN1
dataa_0[7] => dataa_0[7]~0.IN1
datab_0[0] => datab_0[0]~7.IN1
datab_0[1] => datab_0[1]~6.IN1
datab_0[2] => datab_0[2]~5.IN1
datab_0[3] => datab_0[3]~4.IN1
datab_0[4] => datab_0[4]~3.IN1
datab_0[5] => datab_0[5]~2.IN1
datab_0[6] => datab_0[6]~1.IN1
datab_0[7] => datab_0[7]~0.IN1
result[0] <= altmult_add:ALTMULT_ADD_component.result
result[1] <= altmult_add:ALTMULT_ADD_component.result
result[2] <= altmult_add:ALTMULT_ADD_component.result
result[3] <= altmult_add:ALTMULT_ADD_component.result
result[4] <= altmult_add:ALTMULT_ADD_component.result
result[5] <= altmult_add:ALTMULT_ADD_component.result
result[6] <= altmult_add:ALTMULT_ADD_component.result
result[7] <= altmult_add:ALTMULT_ADD_component.result
result[8] <= altmult_add:ALTMULT_ADD_component.result
result[9] <= altmult_add:ALTMULT_ADD_component.result
result[10] <= altmult_add:ALTMULT_ADD_component.result
result[11] <= altmult_add:ALTMULT_ADD_component.result
result[12] <= altmult_add:ALTMULT_ADD_component.result
result[13] <= altmult_add:ALTMULT_ADD_component.result
result[14] <= altmult_add:ALTMULT_ADD_component.result
result[15] <= altmult_add:ALTMULT_ADD_component.result


|Diff_io_top|mult:mult_inst|altmult_add:ALTMULT_ADD_component
dataa[0] => mult_add_v4n1:auto_generated.dataa[0]
dataa[1] => mult_add_v4n1:auto_generated.dataa[1]
dataa[2] => mult_add_v4n1:auto_generated.dataa[2]
dataa[3] => mult_add_v4n1:auto_generated.dataa[3]
dataa[4] => mult_add_v4n1:auto_generated.dataa[4]
dataa[5] => mult_add_v4n1:auto_generated.dataa[5]
dataa[6] => mult_add_v4n1:auto_generated.dataa[6]
dataa[7] => mult_add_v4n1:auto_generated.dataa[7]
datab[0] => mult_add_v4n1:auto_generated.datab[0]
datab[1] => mult_add_v4n1:auto_generated.datab[1]
datab[2] => mult_add_v4n1:auto_generated.datab[2]
datab[3] => mult_add_v4n1:auto_generated.datab[3]
datab[4] => mult_add_v4n1:auto_generated.datab[4]
datab[5] => mult_add_v4n1:auto_generated.datab[5]
datab[6] => mult_add_v4n1:auto_generated.datab[6]
datab[7] => mult_add_v4n1:auto_generated.datab[7]
addnsub1 => ~NO_FANOUT~
addnsub3 => ~NO_FANOUT~
signa => ~NO_FANOUT~
signb => ~NO_FANOUT~
clock0 => mult_add_v4n1:auto_generated.clock0
clock1 => ~NO_FANOUT~
clock2 => ~NO_FANOUT~
clock3 => ~NO_FANOUT~
ena0 => ~NO_FANOUT~
ena1 => ~NO_FANOUT~
ena2 => ~NO_FANOUT~
ena3 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
aclr2 => ~NO_FANOUT~
aclr3 => ~NO_FANOUT~
scanina[0] => ~NO_FANOUT~
scanina[1] => ~NO_FANOUT~
scanina[2] => ~NO_FANOUT~
scanina[3] => ~NO_FANOUT~
scanina[4] => ~NO_FANOUT~
scanina[5] => ~NO_FANOUT~
scanina[6] => ~NO_FANOUT~
scanina[7] => ~NO_FANOUT~
sourcea[0] => ~NO_FANOUT~
scaninb[0] => ~NO_FANOUT~
scaninb[1] => ~NO_FANOUT~
scaninb[2] => ~NO_FANOUT~
scaninb[3] => ~NO_FANOUT~
scaninb[4] => ~NO_FANOUT~
scaninb[5] => ~NO_FANOUT~
scaninb[6] => ~NO_FANOUT~
scaninb[7] => ~NO_FANOUT~
sourceb[0] => ~NO_FANOUT~
mult01_round => ~NO_FANOUT~
mult23_round => ~NO_FANOUT~
addnsub1_round => ~NO_FANOUT~
addnsub3_round => ~NO_FANOUT~
mult01_saturation => ~NO_FANOUT~
mult23_saturation => ~NO_FANOUT~
result[0] <= mult_add_v4n1:auto_generated.result[0]
result[1] <= mult_add_v4n1:auto_generated.result[1]
result[2] <= mult_add_v4n1:auto_generated.result[2]
result[3] <= mult_add_v4n1:auto_generated.result[3]
result[4] <= mult_add_v4n1:auto_generated.result[4]
result[5] <= mult_add_v4n1:auto_generated.result[5]
result[6] <= mult_add_v4n1:auto_generated.result[6]
result[7] <= mult_add_v4n1:auto_generated.result[7]
result[8] <= mult_add_v4n1:auto_generated.result[8]
result[9] <= mult_add_v4n1:auto_generated.result[9]
result[10] <= mult_add_v4n1:auto_generated.result[10]
result[11] <= mult_add_v4n1:auto_generated.result[11]
result[12] <= mult_add_v4n1:auto_generated.result[12]
result[13] <= mult_add_v4n1:auto_generated.result[13]
result[14] <= mult_add_v4n1:auto_generated.result[14]
result[15] <= mult_add_v4n1:auto_generated.result[15]
scanouta[0] <= <UNC>
scanouta[1] <= <UNC>
scanouta[2] <= <UNC>
scanouta[3] <= <UNC>
scanouta[4] <= <UNC>
scanouta[5] <= <UNC>
scanouta[6] <= <UNC>
scanouta[7] <= <UNC>
scanoutb[0] <= <UNC>
scanoutb[1] <= <UNC>
scanoutb[2] <= <UNC>
scanoutb[3] <= <UNC>
scanoutb[4] <= <UNC>
scanoutb[5] <= <UNC>
scanoutb[6] <= <UNC>
scanoutb[7] <= <UNC>
mult0_is_saturated <= <UNC>
mult1_is_saturated <= <UNC>
mult2_is_saturated <= <UNC>
mult3_is_saturated <= <UNC>


|Diff_io_top|mult:mult_inst|altmult_add:ALTMULT_ADD_component|mult_add_v4n1:auto_generated
clock0 => mac_mult1.CLK
clock0 => mac_out2.CLK
dataa[0] => mac_mult1.DATAA
dataa[1] => mac_mult1.DATAA1
dataa[2] => mac_mult1.DATAA2
dataa[3] => mac_mult1.DATAA3
dataa[4] => mac_mult1.DATAA4
dataa[5] => mac_mult1.DATAA5
dataa[6] => mac_mult1.DATAA6
dataa[7] => mac_mult1.DATAA7
datab[0] => mac_mult1.DATAB
datab[1] => mac_mult1.DATAB1
datab[2] => mac_mult1.DATAB2
datab[3] => mac_mult1.DATAB3
datab[4] => mac_mult1.DATAB4
datab[5] => mac_mult1.DATAB5
datab[6] => mac_mult1.DATAB6
datab[7] => mac_mult1.DATAB7
result[0] <= mac_out2.DATAOUT
result[1] <= mac_out2.DATAOUT1
result[2] <= mac_out2.DATAOUT2
result[3] <= mac_out2.DATAOUT3
result[4] <= mac_out2.DATAOUT4
result[5] <= mac_out2.DATAOUT5
result[6] <= mac_out2.DATAOUT6
result[7] <= mac_out2.DATAOUT7
result[8] <= mac_out2.DATAOUT8
result[9] <= mac_out2.DATAOUT9
result[10] <= mac_out2.DATAOUT10
result[11] <= mac_out2.DATAOUT11
result[12] <= mac_out2.DATAOUT12
result[13] <= mac_out2.DATAOUT13
result[14] <= mac_out2.DATAOUT14
result[15] <= mac_out2.DATAOUT15


|Diff_io_top|lvds_tx:lvds_tx_inst
tx_in[0] => tx_in[0]~15.IN1
tx_in[1] => tx_in[1]~14.IN1
tx_in[2] => tx_in[2]~13.IN1
tx_in[3] => tx_in[3]~12.IN1
tx_in[4] => tx_in[4]~11.IN1
tx_in[5] => tx_in[5]~10.IN1
tx_in[6] => tx_in[6]~9.IN1
tx_in[7] => tx_in[7]~8.IN1
tx_in[8] => tx_in[8]~7.IN1
tx_in[9] => tx_in[9]~6.IN1
tx_in[10] => tx_in[10]~5.IN1
tx_in[11] => tx_in[11]~4.IN1
tx_in[12] => tx_in[12]~3.IN1
tx_in[13] => tx_in[13]~2.IN1
tx_in[14] => tx_in[14]~1.IN1
tx_in[15] => tx_in[15]~0.IN1
tx_inclock => tx_inclock~0.IN1
tx_out[0] <= altlvds_tx:altlvds_tx_component.tx_out
tx_out[1] <= altlvds_tx:altlvds_tx_component.tx_out
tx_outclock <= altlvds_tx:altlvds_tx_component.tx_outclock


|Diff_io_top|lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component
tx_in[0] => txreg[0].DATAIN
tx_in[1] => txreg[1].DATAIN
tx_in[2] => txreg[2].DATAIN
tx_in[3] => txreg[3].DATAIN
tx_in[4] => txreg[4].DATAIN
tx_in[5] => txreg[5].DATAIN
tx_in[6] => txreg[6].DATAIN
tx_in[7] => txreg[7].DATAIN
tx_in[8] => txreg[8].DATAIN
tx_in[9] => txreg[9].DATAIN
tx_in[10] => txreg[10].DATAIN
tx_in[11] => txreg[11].DATAIN
tx_in[12] => txreg[12].DATAIN
tx_in[13] => txreg[13].DATAIN
tx_in[14] => txreg[14].DATAIN
tx_in[15] => txreg[15].DATAIN
tx_inclock => pll.CLK
tx_inclock => txreg[15].CLK
tx_inclock => txreg[14].CLK
tx_inclock => txreg[13].CLK
tx_inclock => txreg[12].CLK
tx_inclock => txreg[11].CLK
tx_inclock => txreg[10].CLK
tx_inclock => txreg[9].CLK
tx_inclock => txreg[8].CLK
tx_inclock => txreg[7].CLK
tx_inclock => txreg[6].CLK
tx_inclock => txreg[5].CLK
tx_inclock => txreg[4].CLK
tx_inclock => txreg[3].CLK
tx_inclock => txreg[2].CLK
tx_inclock => txreg[1].CLK
tx_inclock => txreg[0].CLK
tx_enable => ~NO_FANOUT~
sync_inclock => ~NO_FANOUT~
tx_pll_enable => pll.ENABLE
pll_areset => ~NO_FANOUT~
tx_out[0] <= tx[0].DATAOUT
tx_out[1] <= tx[1].DATAOUT
tx_outclock <= outclock_tx.DATAOUT
tx_coreclock <= pll.CLK2
tx_locked <= <UNC>