diff_io_top.fit.eqn

Altera FPGA CPLD设计高级篇电子书籍

--H1L7Q is mult:mult_inst|altmult_add:ALTMULT_ADD_component|mult_add_v4n1:auto_generated|mac_mult1~5 at DSPMULT_X10_Y29_N0
H1L7Q = GND;


--E1_rxreg[0] is lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rxreg[0] at LC_X3_Y29_N8
--operation mode is normal

E1_rxreg[0]_sload_eqn = E1_rx[0];
E1_rxreg[0] = DFFEA(E1_rxreg[0]_sload_eqn, GLOBAL(E1_rx_outclock), VCC, , , , );


--E1_rxreg[1] is lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rxreg[1] at LC_X3_Y29_N2
--operation mode is normal

E1_rxreg[1]_sload_eqn = E1L02;
E1_rxreg[1] = DFFEA(E1_rxreg[1]_sload_eqn, GLOBAL(E1_rx_outclock), VCC, , , , );


--E1_rxreg[2] is lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rxreg[2] at LC_X2_Y29_N8
--operation mode is normal

E1_rxreg[2]_sload_eqn = E1L12;
E1_rxreg[2] = DFFEA(E1_rxreg[2]_sload_eqn, GLOBAL(E1_rx_outclock), VCC, , , , );


--E1_rxreg[3] is lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rxreg[3] at LC_X2_Y29_N9
--operation mode is normal

E1_rxreg[3]_sload_eqn = E1L22;
E1_rxreg[3] = DFFEA(E1_rxreg[3]_sload_eqn, GLOBAL(E1_rx_outclock), VCC, , , , );


--E1_rxreg[4] is lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rxreg[4] at LC_X2_Y29_N5
--operation mode is normal

E1_rxreg[4]_sload_eqn = E1L32;
E1_rxreg[4] = DFFEA(E1_rxreg[4]_sload_eqn, GLOBAL(E1_rx_outclock), VCC, , , , );


--E1_rxreg[5] is lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rxreg[5] at LC_X2_Y29_N2
--operation mode is normal

E1_rxreg[5]_sload_eqn = E1L42;
E1_rxreg[5] = DFFEA(E1_rxreg[5]_sload_eqn, GLOBAL(E1_rx_outclock), VCC, , , , );


--E1_rxreg[6] is lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rxreg[6] at LC_X2_Y29_N4
--operation mode is normal

E1_rxreg[6]_sload_eqn = E1L52;
E1_rxreg[6] = DFFEA(E1_rxreg[6]_sload_eqn, GLOBAL(E1_rx_outclock), VCC, , , , );


--E1_rxreg[7] is lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rxreg[7] at LC_X2_Y29_N6
--operation mode is normal

E1_rxreg[7]_sload_eqn = E1L62;
E1_rxreg[7] = DFFEA(E1_rxreg[7]_sload_eqn, GLOBAL(E1_rx_outclock), VCC, , , , );


--E1_rxreg[8] is lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rxreg[8] at LC_X3_Y30_N3
--operation mode is normal

E1_rxreg[8]_sload_eqn = E1_rx[1];
E1_rxreg[8] = DFFEA(E1_rxreg[8]_sload_eqn, GLOBAL(E1_rx_outclock), VCC, , , , );


--E1_rxreg[9] is lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rxreg[9] at LC_X3_Y30_N7
--operation mode is normal

E1_rxreg[9]_sload_eqn = E1L92;
E1_rxreg[9] = DFFEA(E1_rxreg[9]_sload_eqn, GLOBAL(E1_rx_outclock), VCC, , , , );


--E1_rxreg[10] is lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rxreg[10] at LC_X3_Y30_N6
--operation mode is normal

E1_rxreg[10]_sload_eqn = E1L03;
E1_rxreg[10] = DFFEA(E1_rxreg[10]_sload_eqn, GLOBAL(E1_rx_outclock), VCC, , , , );


--E1_rxreg[11] is lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rxreg[11] at LC_X3_Y30_N5
--operation mode is normal

E1_rxreg[11]_sload_eqn = E1L13;
E1_rxreg[11] = DFFEA(E1_rxreg[11]_sload_eqn, GLOBAL(E1_rx_outclock), VCC, , , , );


--E1_rxreg[12] is lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rxreg[12] at LC_X3_Y30_N8
--operation mode is normal

E1_rxreg[12]_sload_eqn = E1L23;
E1_rxreg[12] = DFFEA(E1_rxreg[12]_sload_eqn, GLOBAL(E1_rx_outclock), VCC, , , , );


--E1_rxreg[13] is lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rxreg[13] at LC_X3_Y30_N9
--operation mode is normal

E1_rxreg[13]_sload_eqn = E1L33;
E1_rxreg[13] = DFFEA(E1_rxreg[13]_sload_eqn, GLOBAL(E1_rx_outclock), VCC, , , , );


--E1_rxreg[14] is lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rxreg[14] at LC_X3_Y30_N2
--operation mode is normal

E1_rxreg[14]_sload_eqn = E1L43;
E1_rxreg[14] = DFFEA(E1_rxreg[14]_sload_eqn, GLOBAL(E1_rx_outclock), VCC, , , , );


--E1_rxreg[15] is lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rxreg[15] at LC_X3_Y30_N4
--operation mode is normal

E1_rxreg[15]_sload_eqn = E1L53;
E1_rxreg[15] = DFFEA(E1_rxreg[15]_sload_eqn, GLOBAL(E1_rx_outclock), VCC, , , , );


--E1_rx[0] is lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rx[0] at SERDESRX_X0_Y29_N4
E1_rx[0] = SERDES_RX.DATAOUT0(.DATAIN(rx_in[0]), .CLK0(GLOBAL(E1_pll)), .ENABLE0(GLOBAL(E1L9)), .ENABLE1(GLOBAL(E1L01)));

--E1L02 is lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rx[0]~DATAOUT1 at SERDESRX_X0_Y29_N4
E1L02 = SERDES_RX.DATAOUT1(.DATAIN(rx_in[0]), .CLK0(GLOBAL(E1_pll)), .ENABLE0(GLOBAL(E1L9)), .ENABLE1(GLOBAL(E1L01)));

--E1L12 is lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rx[0]~DATAOUT2 at SERDESRX_X0_Y29_N4
E1L12 = SERDES_RX.DATAOUT2(.DATAIN(rx_in[0]), .CLK0(GLOBAL(E1_pll)), .ENABLE0(GLOBAL(E1L9)), .ENABLE1(GLOBAL(E1L01)));

--E1L22 is lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rx[0]~DATAOUT3 at SERDESRX_X0_Y29_N4
E1L22 = SERDES_RX.DATAOUT3(.DATAIN(rx_in[0]), .CLK0(GLOBAL(E1_pll)), .ENABLE0(GLOBAL(E1L9)), .ENABLE1(GLOBAL(E1L01)));

--E1L32 is lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rx[0]~DATAOUT4 at SERDESRX_X0_Y29_N4
E1L32 = SERDES_RX.DATAOUT4(.DATAIN(rx_in[0]), .CLK0(GLOBAL(E1_pll)), .ENABLE0(GLOBAL(E1L9)), .ENABLE1(GLOBAL(E1L01)));

--E1L42 is lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rx[0]~DATAOUT5 at SERDESRX_X0_Y29_N4
E1L42 = SERDES_RX.DATAOUT5(.DATAIN(rx_in[0]), .CLK0(GLOBAL(E1_pll)), .ENABLE0(GLOBAL(E1L9)), .ENABLE1(GLOBAL(E1L01)));

--E1L52 is lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rx[0]~DATAOUT6 at SERDESRX_X0_Y29_N4
E1L52 = SERDES_RX.DATAOUT6(.DATAIN(rx_in[0]), .CLK0(GLOBAL(E1_pll)), .ENABLE0(GLOBAL(E1L9)), .ENABLE1(GLOBAL(E1L01)));

--E1L62 is lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rx[0]~DATAOUT7 at SERDESRX_X0_Y29_N4
E1L62 = SERDES_RX.DATAOUT7(.DATAIN(rx_in[0]), .CLK0(GLOBAL(E1_pll)), .ENABLE0(GLOBAL(E1L9)), .ENABLE1(GLOBAL(E1L01)));


--E1_rx[1] is lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rx[1] at SERDESRX_X0_Y30_N4
E1_rx[1] = SERDES_RX.DATAOUT0(.DATAIN(rx_in[1]), .CLK0(GLOBAL(E1_pll)), .ENABLE0(GLOBAL(E1L9)), .ENABLE1(GLOBAL(E1L01)));

--E1L92 is lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rx[1]~DATAOUT1 at SERDESRX_X0_Y30_N4
E1L92 = SERDES_RX.DATAOUT1(.DATAIN(rx_in[1]), .CLK0(GLOBAL(E1_pll)), .ENABLE0(GLOBAL(E1L9)), .ENABLE1(GLOBAL(E1L01)));

--E1L03 is lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rx[1]~DATAOUT2 at SERDESRX_X0_Y30_N4
E1L03 = SERDES_RX.DATAOUT2(.DATAIN(rx_in[1]), .CLK0(GLOBAL(E1_pll)), .ENABLE0(GLOBAL(E1L9)), .ENABLE1(GLOBAL(E1L01)));

--E1L13 is lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rx[1]~DATAOUT3 at SERDESRX_X0_Y30_N4
E1L13 = SERDES_RX.DATAOUT3(.DATAIN(rx_in[1]), .CLK0(GLOBAL(E1_pll)), .ENABLE0(GLOBAL(E1L9)), .ENABLE1(GLOBAL(E1L01)));

--E1L23 is lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rx[1]~DATAOUT4 at SERDESRX_X0_Y30_N4
E1L23 = SERDES_RX.DATAOUT4(.DATAIN(rx_in[1]), .CLK0(GLOBAL(E1_pll)), .ENABLE0(GLOBAL(E1L9)), .ENABLE1(GLOBAL(E1L01)));

--E1L33 is lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rx[1]~DATAOUT5 at SERDESRX_X0_Y30_N4
E1L33 = SERDES_RX.DATAOUT5(.DATAIN(rx_in[1]), .CLK0(GLOBAL(E1_pll)), .ENABLE0(GLOBAL(E1L9)), .ENABLE1(GLOBAL(E1L01)));

--E1L43 is lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rx[1]~DATAOUT6 at SERDESRX_X0_Y30_N4
E1L43 = SERDES_RX.DATAOUT6(.DATAIN(rx_in[1]), .CLK0(GLOBAL(E1_pll)), .ENABLE0(GLOBAL(E1L9)), .ENABLE1(GLOBAL(E1L01)));

--E1L53 is lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rx[1]~DATAOUT7 at SERDESRX_X0_Y30_N4
E1L53 = SERDES_RX.DATAOUT7(.DATAIN(rx_in[1]), .CLK0(GLOBAL(E1_pll)), .ENABLE0(GLOBAL(E1L9)), .ENABLE1(GLOBAL(E1L01)));


--rx_data_align is rx_data_align at PIN_N27
--operation mode is input

rx_data_align = INPUT();


--rx_inclock is rx_inclock at PIN_P25
--operation mode is input

rx_inclock = INPUT();


--rx_in[0] is rx_in[0] at PIN_H26
--operation mode is input

rx_in[0] = INPUT();


--rx_in[1] is rx_in[1] at PIN_G27
--operation mode is input

rx_in[1] = INPUT();


--rx_locked is rx_locked at PIN_N28
--operation mode is output

rx_locked = OUTPUT(!E1L61);


--tx_out[1] is tx_out[1] at PIN_L23
--operation mode is output

tx_out[1] = OUTPUT(F1_tx_out[1]);


--tx_out[0] is tx_out[0] at PIN_L22
--operation mode is output

tx_out[0] = OUTPUT(F1_tx_out[0]);


--tx_outclock is tx_outclock at PIN_K21
--operation mode is output

tx_outclock = OUTPUT(F1_tx_outclock);


--A1L41 is tx_out[1](n) at PIN_L24
--operation mode is output

A1L41 = LVDS_OUTPUT();


--A1L21 is tx_out[0](n) at PIN_L21
--operation mode is output

A1L21 = LVDS_OUTPUT();


--A1L61 is tx_outclock(n) at PIN_K22
--operation mode is output

A1L61 = LVDS_OUTPUT();


--A1L8 is rx_inclock(n) at PIN_P26
--operation mode is input

A1L8 = LVDS_INPUT();


--A1L4 is rx_in[0](n) at PIN_H25
--operation mode is input

A1L4 = LVDS_INPUT();


--A1L6 is rx_in[1](n) at PIN_G28
--operation mode is input

A1L6 = LVDS_INPUT();