diff_io_top.fit.eqn

Altera FPGA CPLD设计高级篇电子书籍

--E1L61 is lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|pll~LOCKED at PLL_1
--This is a fast PLL. The LOCKED output for a fast PLL is active low and not active high.
E1L61 = PLL.LOCKED(.ENA(), .COMPARATOR(rx_data_align), .INCLK(rx_inclock));

--E1L9 is lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|pll~ENAOUT0 at PLL_1
E1L9 = PLL.ENABLE0(.ENA(), .COMPARATOR(rx_data_align), .INCLK(rx_inclock));

--E1L01 is lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|pll~ENAOUT1 at PLL_1
E1L01 = PLL.ENABLE1(.ENA(), .COMPARATOR(rx_data_align), .INCLK(rx_inclock));

--E1_pll is lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|pll at PLL_1
E1_pll = PLL.CLK0(.ENA(), .COMPARATOR(rx_data_align), .INCLK(rx_inclock));

--E1_rx_outclock is lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rx_outclock at PLL_1
E1_rx_outclock = PLL.CLK2(.ENA(), .COMPARATOR(rx_data_align), .INCLK(rx_inclock));


--F1_tx_out[1] is lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|tx_out[1] at SERDESTX_X0_Y28_N5
F1_tx_out[1]_data_in = DATA(F1_txreg[8], F1_txreg[9], F1_txreg[10], F1_txreg[11], F1_txreg[12], F1_txreg[13], F1_txreg[14], F1_txreg[15]);
F1_tx_out[1] = SERDES_TX.DATAOUT(.CLK0(GLOBAL(E1_pll)), .ENABLE0(GLOBAL(E1L01)), F1_tx_out[1]_data_in);


--F1_tx_out[0] is lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|tx_out[0] at SERDESTX_X0_Y29_N5
F1_tx_out[0]_data_in = DATA(F1_txreg[0], F1_txreg[1], F1_txreg[2], F1_txreg[3], F1_txreg[4], F1_txreg[5], F1_txreg[6], F1_txreg[7]);
F1_tx_out[0] = SERDES_TX.DATAOUT(.CLK0(GLOBAL(E1_pll)), .ENABLE0(GLOBAL(E1L01)), F1_tx_out[0]_data_in);


--F1_tx_outclock is lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|tx_outclock at SERDESTX_X0_Y30_N5
F1_tx_outclock_data_in = DATA(VCC, VCC, GND, GND, GND, GND, VCC, VCC);
F1_tx_outclock = SERDES_TX.DATAOUT(.CLK0(GLOBAL(E1_pll)), .ENABLE0(GLOBAL(E1L01)), F1_tx_outclock_data_in);


--F1_txreg[8] is lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[8] at LC_X3_Y28_N5
--operation mode is normal

F1_txreg[8]_sload_eqn = H1_result[8];
F1_txreg[8] = DFFEA(F1_txreg[8]_sload_eqn, GLOBAL(E1_rx_outclock), VCC, , , , );


--F1_txreg[9] is lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[9] at LC_X3_Y28_N2
--operation mode is normal

F1_txreg[9]_sload_eqn = H1_result[9];
F1_txreg[9] = DFFEA(F1_txreg[9]_sload_eqn, GLOBAL(E1_rx_outclock), VCC, , , , );


--F1_txreg[10] is lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[10] at LC_X3_Y28_N9
--operation mode is normal

F1_txreg[10]_sload_eqn = H1_result[10];
F1_txreg[10] = DFFEA(F1_txreg[10]_sload_eqn, GLOBAL(E1_rx_outclock), VCC, , , , );


--F1_txreg[11] is lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[11] at LC_X3_Y28_N3
--operation mode is normal

F1_txreg[11]_sload_eqn = H1_result[11];
F1_txreg[11] = DFFEA(F1_txreg[11]_sload_eqn, GLOBAL(E1_rx_outclock), VCC, , , , );


--F1_txreg[12] is lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[12] at LC_X3_Y28_N6
--operation mode is normal

F1_txreg[12]_sload_eqn = H1_result[12];
F1_txreg[12] = DFFEA(F1_txreg[12]_sload_eqn, GLOBAL(E1_rx_outclock), VCC, , , , );


--F1_txreg[13] is lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[13] at LC_X3_Y28_N8
--operation mode is normal

F1_txreg[13]_sload_eqn = H1_result[13];
F1_txreg[13] = DFFEA(F1_txreg[13]_sload_eqn, GLOBAL(E1_rx_outclock), VCC, , , , );


--F1_txreg[14] is lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[14] at LC_X3_Y28_N4
--operation mode is normal

F1_txreg[14]_lut_out = H1_result[14];
F1_txreg[14] = DFFEA(F1_txreg[14]_lut_out, GLOBAL(E1_rx_outclock), VCC, , , , );


--F1_txreg[15] is lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[15] at LC_X3_Y28_N7
--operation mode is normal

F1_txreg[15]_sload_eqn = H1_result[15];
F1_txreg[15] = DFFEA(F1_txreg[15]_sload_eqn, GLOBAL(E1_rx_outclock), VCC, , , , );


--F1_txreg[0] is lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[0] at LC_X3_Y29_N0
--operation mode is normal

F1_txreg[0]_sload_eqn = H1_result[0];
F1_txreg[0] = DFFEA(F1_txreg[0]_sload_eqn, GLOBAL(E1_rx_outclock), VCC, , , , );


--F1_txreg[1] is lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[1] at LC_X3_Y29_N9
--operation mode is normal

F1_txreg[1]_sload_eqn = H1_result[1];
F1_txreg[1] = DFFEA(F1_txreg[1]_sload_eqn, GLOBAL(E1_rx_outclock), VCC, , , , );


--F1_txreg[2] is lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[2] at LC_X3_Y29_N5
--operation mode is normal

F1_txreg[2]_sload_eqn = H1_result[2];
F1_txreg[2] = DFFEA(F1_txreg[2]_sload_eqn, GLOBAL(E1_rx_outclock), VCC, , , , );


--F1_txreg[3] is lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[3] at LC_X3_Y29_N3
--operation mode is normal

F1_txreg[3]_sload_eqn = H1_result[3];
F1_txreg[3] = DFFEA(F1_txreg[3]_sload_eqn, GLOBAL(E1_rx_outclock), VCC, , , , );


--F1_txreg[4] is lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[4] at LC_X3_Y29_N6
--operation mode is normal

F1_txreg[4]_sload_eqn = H1_result[4];
F1_txreg[4] = DFFEA(F1_txreg[4]_sload_eqn, GLOBAL(E1_rx_outclock), VCC, , , , );


--F1_txreg[5] is lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[5] at LC_X3_Y29_N1
--operation mode is normal

F1_txreg[5]_sload_eqn = H1_result[5];
F1_txreg[5] = DFFEA(F1_txreg[5]_sload_eqn, GLOBAL(E1_rx_outclock), VCC, , , , );


--F1_txreg[6] is lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[6] at LC_X3_Y29_N4
--operation mode is normal

F1_txreg[6]_lut_out = H1_result[6];
F1_txreg[6] = DFFEA(F1_txreg[6]_lut_out, GLOBAL(E1_rx_outclock), VCC, , , , );


--F1_txreg[7] is lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[7] at LC_X3_Y29_N7
--operation mode is normal

F1_txreg[7]_lut_out = H1_result[7];
F1_txreg[7] = DFFEA(F1_txreg[7]_lut_out, GLOBAL(E1_rx_outclock), VCC, , , , );


--H1_result[0] is mult:mult_inst|altmult_add:ALTMULT_ADD_component|mult_add_v4n1:auto_generated|result[0] at DSPOUT_X11_Y23_N0
--DSP Block Operation Mode: Simple Multiplier (9-bit)
H1_result[0] = H1_mac_mult1;

--H1_result[1] is mult:mult_inst|altmult_add:ALTMULT_ADD_component|mult_add_v4n1:auto_generated|result[1] at DSPOUT_X11_Y23_N0
H1_result[1] = H1L8Q;

--H1_result[2] is mult:mult_inst|altmult_add:ALTMULT_ADD_component|mult_add_v4n1:auto_generated|result[2] at DSPOUT_X11_Y23_N0
H1_result[2] = H1L9Q;

--H1_result[3] is mult:mult_inst|altmult_add:ALTMULT_ADD_component|mult_add_v4n1:auto_generated|result[3] at DSPOUT_X11_Y23_N0
H1_result[3] = H1L01Q;

--H1_result[4] is mult:mult_inst|altmult_add:ALTMULT_ADD_component|mult_add_v4n1:auto_generated|result[4] at DSPOUT_X11_Y23_N0
H1_result[4] = H1L11Q;

--H1_result[5] is mult:mult_inst|altmult_add:ALTMULT_ADD_component|mult_add_v4n1:auto_generated|result[5] at DSPOUT_X11_Y23_N0
H1_result[5] = H1L21Q;

--H1_result[6] is mult:mult_inst|altmult_add:ALTMULT_ADD_component|mult_add_v4n1:auto_generated|result[6] at DSPOUT_X11_Y23_N0
H1_result[6] = H1L31Q;

--H1_result[7] is mult:mult_inst|altmult_add:ALTMULT_ADD_component|mult_add_v4n1:auto_generated|result[7] at DSPOUT_X11_Y23_N0
H1_result[7] = H1L41Q;

--H1_result[8] is mult:mult_inst|altmult_add:ALTMULT_ADD_component|mult_add_v4n1:auto_generated|result[8] at DSPOUT_X11_Y23_N0
H1_result[8] = H1L51Q;

--H1_result[9] is mult:mult_inst|altmult_add:ALTMULT_ADD_component|mult_add_v4n1:auto_generated|result[9] at DSPOUT_X11_Y23_N0
H1_result[9] = H1L61Q;

--H1_result[10] is mult:mult_inst|altmult_add:ALTMULT_ADD_component|mult_add_v4n1:auto_generated|result[10] at DSPOUT_X11_Y23_N0
H1_result[10] = H1L71Q;

--H1_result[11] is mult:mult_inst|altmult_add:ALTMULT_ADD_component|mult_add_v4n1:auto_generated|result[11] at DSPOUT_X11_Y23_N0
H1_result[11] = H1L81Q;

--H1_result[12] is mult:mult_inst|altmult_add:ALTMULT_ADD_component|mult_add_v4n1:auto_generated|result[12] at DSPOUT_X11_Y23_N0
H1_result[12] = H1L91Q;

--H1_result[13] is mult:mult_inst|altmult_add:ALTMULT_ADD_component|mult_add_v4n1:auto_generated|result[13] at DSPOUT_X11_Y23_N0
H1_result[13] = H1L02Q;

--H1_result[14] is mult:mult_inst|altmult_add:ALTMULT_ADD_component|mult_add_v4n1:auto_generated|result[14] at DSPOUT_X11_Y23_N0
H1_result[14] = H1L12Q;

--H1_result[15] is mult:mult_inst|altmult_add:ALTMULT_ADD_component|mult_add_v4n1:auto_generated|result[15] at DSPOUT_X11_Y23_N0
H1_result[15] = H1L22Q;


--H1_mac_mult1 is mult:mult_inst|altmult_add:ALTMULT_ADD_component|mult_add_v4n1:auto_generated|mac_mult1 at DSPMULT_X10_Y29_N0
--DSP Block Multiplier Base Width: 9-bits
H1_mac_mult1_a_data = DATA(E1_rxreg[7], E1_rxreg[6], E1_rxreg[5], E1_rxreg[4], E1_rxreg[3], E1_rxreg[2], E1_rxreg[1], E1_rxreg[0]);
H1_mac_mult1_a_reg = DFFE(H1_mac_mult1_a_data, GLOBAL(E1_rx_outclock), , , );
H1_mac_mult1_a_rep = UNSIGNED(H1_mac_mult1_a_reg);
H1_mac_mult1_b_data = DATA(E1_rxreg[15], E1_rxreg[14], E1_rxreg[13], E1_rxreg[12], E1_rxreg[11], E1_rxreg[10], E1_rxreg[9], E1_rxreg[8]);
H1_mac_mult1_b_reg = DFFE(H1_mac_mult1_b_data, GLOBAL(E1_rx_outclock), , , );
H1_mac_mult1_b_rep = UNSIGNED(H1_mac_mult1_b_reg);
H1_mac_mult1_result = H1_mac_mult1_a_rep * H1_mac_mult1_b_rep;
H1_mac_mult1_result_reg = DFFE(H1_mac_mult1_result, GLOBAL(E1_rx_outclock), , , );
H1_mac_mult1 = H1_mac_mult1_result_reg[0];

--H1L8Q is mult:mult_inst|altmult_add:ALTMULT_ADD_component|mult_add_v4n1:auto_generated|mac_mult1~DATAOUT1 at DSPMULT_X10_Y29_N0
H1L8Q = H1_mac_mult1_result_reg[1];

--H1L9Q is mult:mult_inst|altmult_add:ALTMULT_ADD_component|mult_add_v4n1:auto_generated|mac_mult1~DATAOUT2 at DSPMULT_X10_Y29_N0
H1L9Q = H1_mac_mult1_result_reg[2];

--H1L01Q is mult:mult_inst|altmult_add:ALTMULT_ADD_component|mult_add_v4n1:auto_generated|mac_mult1~DATAOUT3 at DSPMULT_X10_Y29_N0
H1L01Q = H1_mac_mult1_result_reg[3];

--H1L11Q is mult:mult_inst|altmult_add:ALTMULT_ADD_component|mult_add_v4n1:auto_generated|mac_mult1~DATAOUT4 at DSPMULT_X10_Y29_N0
H1L11Q = H1_mac_mult1_result_reg[4];

--H1L21Q is mult:mult_inst|altmult_add:ALTMULT_ADD_component|mult_add_v4n1:auto_generated|mac_mult1~DATAOUT5 at DSPMULT_X10_Y29_N0
H1L21Q = H1_mac_mult1_result_reg[5];

--H1L31Q is mult:mult_inst|altmult_add:ALTMULT_ADD_component|mult_add_v4n1:auto_generated|mac_mult1~DATAOUT6 at DSPMULT_X10_Y29_N0
H1L31Q = H1_mac_mult1_result_reg[6];

--H1L41Q is mult:mult_inst|altmult_add:ALTMULT_ADD_component|mult_add_v4n1:auto_generated|mac_mult1~DATAOUT7 at DSPMULT_X10_Y29_N0
H1L41Q = H1_mac_mult1_result_reg[7];

--H1L51Q is mult:mult_inst|altmult_add:ALTMULT_ADD_component|mult_add_v4n1:auto_generated|mac_mult1~DATAOUT8 at DSPMULT_X10_Y29_N0
H1L51Q = H1_mac_mult1_result_reg[8];

--H1L61Q is mult:mult_inst|altmult_add:ALTMULT_ADD_component|mult_add_v4n1:auto_generated|mac_mult1~DATAOUT9 at DSPMULT_X10_Y29_N0
H1L61Q = H1_mac_mult1_result_reg[9];

--H1L71Q is mult:mult_inst|altmult_add:ALTMULT_ADD_component|mult_add_v4n1:auto_generated|mac_mult1~DATAOUT10 at DSPMULT_X10_Y29_N0
H1L71Q = H1_mac_mult1_result_reg[10];

--H1L81Q is mult:mult_inst|altmult_add:ALTMULT_ADD_component|mult_add_v4n1:auto_generated|mac_mult1~DATAOUT11 at DSPMULT_X10_Y29_N0
H1L81Q = H1_mac_mult1_result_reg[11];

--H1L91Q is mult:mult_inst|altmult_add:ALTMULT_ADD_component|mult_add_v4n1:auto_generated|mac_mult1~DATAOUT12 at DSPMULT_X10_Y29_N0
H1L91Q = H1_mac_mult1_result_reg[12];

--H1L02Q is mult:mult_inst|altmult_add:ALTMULT_ADD_component|mult_add_v4n1:auto_generated|mac_mult1~DATAOUT13 at DSPMULT_X10_Y29_N0
H1L02Q = H1_mac_mult1_result_reg[13];

--H1L12Q is mult:mult_inst|altmult_add:ALTMULT_ADD_component|mult_add_v4n1:auto_generated|mac_mult1~DATAOUT14 at DSPMULT_X10_Y29_N0
H1L12Q = H1_mac_mult1_result_reg[14];

--H1L22Q is mult:mult_inst|altmult_add:ALTMULT_ADD_component|mult_add_v4n1:auto_generated|mac_mult1~DATAOUT15 at DSPMULT_X10_Y29_N0
H1L22Q = H1_mac_mult1_result_reg[15];

--H1L6Q is mult:mult_inst|altmult_add:ALTMULT_ADD_component|mult_add_v4n1:auto_generated|mac_mult1~4 at DSPMULT_X10_Y29_N0
H1L6Q = GND;