fir_top_sim.vhd

Altera FPGA CPLD设计高级篇电子书籍

LIBRARY ieee;                              
USE ieee.std_logic_1164.all;               
USE ieee.std_logic_arith.all; 
USE ieee.std_logic_unsigned.all;
--library leaf_lib;
--USE leaf_lib.LEAF_NODES_PACK.all;

entity fir_top is 
generic(	DATA_WIDTH: integer := 12;

		OUT_WIDTH : integer := 27
	);
port (	clock	:in std_logic;
	rst	:in std_logic;
	data_in	:in std_logic_vector(DATA_WIDTH-1 downto 0) ;
	done	:out std_logic;
	rdy_to_ld	:out std_logic;
	fir_result	:out std_logic_vector(OUT_WIDTH-1 downto 0) 
	); 
end fir_top;

architecture only of fir_top is
	component fir_top_st 
	generic(
		DATA_WIDTH   : integer := 12;
		COEF_WIDTH   : integer := 10;
		ACCUM_WIDTH  : integer := 27		);
	port(
		 clk: in std_logic;
		 rst: in std_logic;
		 data_in: in std_logic_vector (DATA_WIDTH-1 downto 0);
		 done: out std_logic;
		 rdy_to_ld: out std_logic;
	 	 fir_result: out std_logic_vector (ACCUM_WIDTH -1 downto 0)
		);
	end component;

begin
	UST : fir_top_st
	PORT MAP (clk =>clock ,
		rst => rst, 
		data_in =>data_in,
		rdy_to_ld =>rdy_to_ld,
		done => done,
		fir_result => fir_result
		);
end;