fir_top.map.rpt

Altera FPGA CPLD设计高级篇电子书籍

+-------------------------------+-------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary                                                                                                                                                                                                                          ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
; Name                                                                                                                                    ; Type ; Mode             ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF                ;
+-----------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+--------------------+
; fir_top_st:fir_top_st_component|ram_lut:Ur0_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_qs41:auto_generated|ALTSYNCRAM ; M4K  ; Simple Dual Port ; 256          ; 13           ; 256          ; 13           ; 3328 ; fir_top_coef_0.mif ;
; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|ALTSYNCRAM ; M4K  ; Simple Dual Port ; 256          ; 13           ; 256          ; 13           ; 3328 ; fir_top_coef_1.mif ;
; fir_top_st:fir_top_st_component|ram_lut:Ur2_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_6m41:auto_generated|ALTSYNCRAM ; M4K  ; Simple Dual Port ; 8            ; 12           ; 8            ; 12           ; 96   ; fir_top_coef_2.mif ;
+-----------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+--------------------+


+----------------------------------------------------------------+
; WYSIWYG Cells                                                  ;
+-----------------------------------------------------------------
; Statistic                                              ; Value ;
+--------------------------------------------------------+-------+
; Number of WYSIWYG cells                                ; 62    ;
; Number of synthesis-generated cells                    ; 603   ;
; Number of WYSIWYG LUTs                                 ; 62    ;
; Number of synthesis-generated LUTs                     ; 54    ;
; Number of WYSIWYG registers                            ; 61    ;
; Number of synthesis-generated registers                ; 599   ;
; Number of cells with combinational logic only          ; 5     ;
; Number of cells with registers only                    ; 549   ;
; Number of cells with combinational logic and registers ; 111   ;
+--------------------------------------------------------+-------+


+----------------------------------------------+
; General Register Statistics                  ;
+-----------------------------------------------
; Statistic                            ; Value ;
+--------------------------------------+-------+
; Number of registers using SCLR       ; 0     ;
; Number of registers using SLOAD      ; 16    ;
; Number of registers using ACLR       ; 14    ;
; Number of registers using ALOAD      ; 0     ;
; Number of registers using CLK_ENABLE ; 27    ;
; Number of registers using OE         ; 0     ;
; Number of registers using PRESET     ; 0     ;
+--------------------------------------+-------+


+--------------------------------+
; Analysis & Synthesis Messages  ;
+--------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.0 Build 187 1/20/2004 SJ Full Version
    Info: Processing started: Thu Feb 19 13:06:18 2004
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off fir_top -c fir_top
Info: Using design file fir_top.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: fir_top-SYN
    Info: Found entity 1: fir_top
Info: Using design file fir_top_st.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: fir_top_st
Info: Using design file ../../../../../../megacore/fir_compiler-v2.7.1/lib/par_ld_ser_tdl_nc.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: par_ld_ser_tdl_nc
Warning: Found the following files while searching for definition of entity par_ld_ser_tdl_nc, but did not use these files because already using a different file containing the entity definition
    Warning: File: ../../../../../../megacore/fir_compiler-v2.7.1/lib_time_limited/par_ld_ser_tdl_nc.v
Info: Using design file ../../../../../../megacore/fir_compiler-v2.7.1/lib/lc_tdl_strat.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: lc_tdl_strat
Warning: Found the following files while searching for definition of entity lc_tdl_strat, but did not use these files because already using a different file containing the entity definition
    Warning: File: ../../../../../../megacore/fir_compiler-v2.7.1/lib_time_limited/lc_tdl_strat.v
Info: Using design file ../../../../../../megacore/fir_compiler-v2.7.1/lib/sym_add_ser.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: sym_add_ser
Warning: Found the following files while searching for definition of entity sym_add_ser, but did not use these files because already using a different file containing the entity definition
    Warning: File: ../../../../../../megacore/fir_compiler-v2.7.1/lib_time_limited/sym_add_ser.v
Info: Using design file ../../../../../../megacore/fir_compiler-v2.7.1/lib/ram_lut.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: ram_lut
Warning: Found the following files while searching for definition of entity ram_lut, but did not use these files because already using a different file containing the entity definition
    Warning: File: ../../../../../../megacore/fir_compiler-v2.7.1/lib_time_limited/ram_lut.v
Info: Using design file ../../../../../../megacore/fir_compiler-v2.7.1/lib/ram_2pt_var.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: ram_2pt_var
Warning: Found the following files while searching for definition of entity ram_2pt_var, but did not use these files because already using a different file containing the entity definition
    Warning: File: ../../../../../../megacore/fir_compiler-v2.7.1/lib_time_limited/ram_2pt_var.v
Info: Found 1 design units and 1 entities in source file ../../../../../../quartus4_0/libraries/megafunctions/altsyncram.tdf
    Info: Found entity 1: altsyncram
Info: Found 1 design units and 1 entities in source file db/altsyncram_qs41.tdf
    Info: Found entity 1: altsyncram_qs41
Info: Found 1 design units and 1 entities in source file db/altsyncram_rs41.tdf
    Info: Found entity 1: altsyncram_rs41
Info: Found 1 design units and 1 entities in source file db/altsyncram_6m41.tdf
    Info: Found entity 1: altsyncram_6m41
Info: Using design file ../../../../../../megacore/fir_compiler-v2.7.1/lib/sadd.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: sadd
Warning: Found the following files while searching for definition of entity sadd, but did not use these files because already using a different file containing the entity definition
    Warning: File: ../../../../../../megacore/fir_compiler-v2.7.1/lib_time_limited/sadd.v
Info: Using design file ../../../../../../megacore/fir_compiler-v2.7.1/lib/mac_tl.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: mac_tl
Warning: Found the following files while searching for definition of entity mac_tl, but did not use these files because already using a different file containing the entity definition
    Warning: File: ../../../../../../megacore/fir_compiler-v2.7.1/lib_time_limited/mac_tl.v
Info: Using design file ../../../../../../megacore/fir_compiler-v2.7.1/lib/scale_accum.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: scale_accum
Warning: Found the following files while searching for definition of entity scale_accum, but did not use these files because already using a different file containing the entity definition
    Warning: File: ../../../../../../megacore/fir_compiler-v2.7.1/lib_time_limited/scale_accum.v
Info: Using design file ../../../../../../megacore/fir_compiler-v2.7.1/lib/ser_shft.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: ser_shft
Warning: Found the following files while searching for definition of entity ser_shft, but did not use these files because already using a different file containing the entity definition
    Warning: File: ../../../../../../megacore/fir_compiler-v2.7.1/lib_time_limited/ser_shft.v
Info: Using design file ../../../../../../megacore/fir_compiler-v2.7.1/lib/scale_shft_comb.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: scale_shft_comb
Warning: Found the following files while searching for definition of entity scale_shft_comb, but did not use these files because already using a different file containing the entity definition
    Warning: File: ../../../../../../megacore/fir_compiler-v2.7.1/lib_time_limited/scale_shft_comb.v
Info: Using design file ../../../../../../megacore/fir_compiler-v2.7.1/lib/ser_ctrl_nc.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: ser_ctrl_nc
Warning: Found the following files while searching for definition of entity ser_ctrl_nc, but did not use these files because already using a different file containing the entity definition
    Warning: File: ../../../../../../megacore/fir_compiler-v2.7.1/lib_time_limited/ser_ctrl_nc.v
Info: Duplicate registers merged to single register
    Info: Duplicate register fir_top_st:fir_top_st_component|sadd:Uaddl_0_n_1_n|res[11]~reg0 merged to single register fir_top_st:fir_top_st_component|sadd:Uaddl_0_n_1_n|res[12]~reg0
    Info: Duplicate register fir_top_st:fir_top_st_component|sadd:Uaddl_0_n_1_n|res[13]~reg0 merged to single register fir_top_st:fir_top_st_component|sadd:Uaddl_0_n_1_n|res[12]~reg0
Warning: Reduced register fir_top_st:fir_top_st_component|sym_add_ser:sym_18_n|c_out with stuck data_in port to stuck value GND
Info: Duplicate registers merged to single register
    Info: Duplicate register fir_top_st:fir_top_st_component|lc_tdl_strat:Utdl_1_n|sft02_n[12] merged to single register fir_top_st:fir_top_st_component|sym_add_ser:sym_18_n|data_out[0]~reg0
Info: Registers with preset signals will power-up high
Info: Implemented 746 device resources after synthesis - the final resource count might be different
    Info: Implemented 14 input pins
    Info: Implemented 29 output pins
    Info: Implemented 665 logic cells
    Info: Implemented 38 RAM segments
Warning: Ignored assignments for entity "lc_tdl" -- entity does not exist in design
Warning: Ignored assignments for entity "lc_tdl_en" -- entity does not exist in design
Warning: Ignored assignments for entity "lc_tdl_mr" -- entity does not exist in design
Warning: Ignored assignments for entity "sadd_lpm" -- entity does not exist in design
Warning: Ignored assignments for entity "tdl_da_lc" -- entity does not exist in design
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 28 warnings
    Info: Processing ended: Thu Feb 19 13:06:27 2004
    Info: Elapsed time: 00:00:09