fir_top.map.rpt

Altera FPGA CPLD设计高级篇电子书籍

Analysis & Synthesis report for fir_top
Thu Feb 19 13:06:27 2004
Version 4.0 Build 187 1/20/2004 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Default Parameter Settings
  5. Hierarchy
  6. Analysis & Synthesis Resource Utilization by Entity
  7. Analysis & Synthesis Equations
  8. Analysis & Synthesis Files Read
  9. Analysis & Synthesis Resource Usage Summary
 10. Analysis & Synthesis RAM Summary
 11. WYSIWYG Cells
 12. General Register Statistics
 13. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2004 Altera Corporation
Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
support information,  device programming or simulation file,  and any other
associated  documentation or information  provided by  Altera  or a partner
under  Altera's   Megafunction   Partnership   Program  may  be  used  only
to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
other  use  of such  megafunction  design,  netlist,  support  information,
device programming or simulation file,  or any other  related documentation
or information  is prohibited  for  any  other purpose,  including, but not
limited to  modification,  reverse engineering,  de-compiling, or use  with
any other  silicon devices,  unless such use is  explicitly  licensed under
a separate agreement with  Altera  or a megafunction partner.  Title to the
intellectual property,  including patents,  copyrights,  trademarks,  trade
secrets,  or maskworks,  embodied in any such megafunction design, netlist,
support  information,  device programming or simulation file,  or any other
related documentation or information provided by  Altera  or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.



+---------------------------------------------------------------------+
; Analysis & Synthesis Summary                                        ;
+-----------------------------+---------------------------------------+
; Analysis & Synthesis Status ; Successful - Thu Feb 19 13:06:27 2004 ;
; Revision Name               ; fir_top                               ;
; Top-level Entity Name       ; fir_top                               ;
; Family                      ; Stratix                               ;
; Total logic elements        ; 665                                   ;
; Total pins                  ; 43                                    ;
; Total memory bits           ; 6,752                                 ;
; DSP block 9-bit elements    ; 0                                     ;
; Total PLLs                  ; 0                                     ;
; Total DLLs                  ; 0                                     ;
+-----------------------------+---------------------------------------+


+----------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                          ;
+-----------------------------------------------------------------------------------------
; Option                                                  ; Setting      ; Default Value ;
+---------------------------------------------------------+--------------+---------------+
; Top-level entity name                                   ; fir_top      ;               ;
; Auto Resource Sharing                                   ; Off          ; Off           ;
; Auto RAM Block Balancing                                ; On           ; On            ;
; Auto Shift Register Replacement                         ; On           ; On            ;
; Auto DSP Block Replacement                              ; On           ; On            ;
; Auto RAM Replacement                                    ; On           ; On            ;
; Auto ROM Replacement                                    ; On           ; On            ;
; Allow register retiming to trade off Tsu/Tco with Fmax  ; On           ; On            ;
; Perform gate-level register retiming                    ; Off          ; Off           ;
; Perform WYSIWYG Primitive Resynthesis                   ; Off          ; Off           ;
; Remove Duplicate Logic                                  ; On           ; On            ;
; Auto Open-Drain Pins                                    ; On           ; On            ;
; Auto Carry Chains                                       ; On           ; On            ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II ; 70           ; 70            ;
; Optimization Technique -- Stratix/Stratix GX            ; Balanced     ; Balanced      ;
; Auto Global Register Control Signals                    ; On           ; On            ;
; Auto Global Clock                                       ; On           ; On            ;
; Limit AHDL Integers to 32 Bits                          ; Off          ; Off           ;
; Ignore SOFT Buffers                                     ; On           ; On            ;
; Ignore LCELL Buffers                                    ; Off          ; Off           ;
; Ignore ROW GLOBAL Buffers                               ; Off          ; Off           ;
; Ignore GLOBAL Buffers                                   ; Off          ; Off           ;
; Ignore CASCADE Buffers                                  ; Off          ; Off           ;
; Ignore CARRY Buffers                                    ; Off          ; Off           ;
; Remove Duplicate Registers                              ; On           ; On            ;
; Remove Redundant Logic Cells                            ; Off          ; Off           ;
; Power-Up Don't Care                                     ; On           ; On            ;
; NOT Gate Push-Back                                      ; On           ; On            ;
; DSP Block Balancing                                     ; Auto         ; Auto          ;
; State Machine Processing                                ; Auto         ; Auto          ;
; Family name                                             ; Stratix      ; Stratix       ;
; VHDL Version                                            ; VHDL93       ; VHDL93        ;
; Verilog Version                                         ; Verilog_2001 ; Verilog_2001  ;
; Preserve fewer node names                               ; On           ; On            ;
; Disk space/compilation speed tradeoff                   ; Normal       ; Normal        ;
; Create Debugging Nodes for IP Cores                     ; off          ; off           ;
+---------------------------------------------------------+--------------+---------------+


+-------------------------------------------------+
; Analysis & Synthesis Default Parameter Settings ;
+--------------------------------------------------
; Name               ; Setting                    ;
+--------------------+----------------------------+
; CARRY_CHAIN        ; MANUAL                     ;
; CASCADE_CHAIN      ; MANUAL                     ;
; OPTIMIZE_FOR_SPEED ; 5                          ;
; STYLE              ; FAST                       ;
+--------------------+----------------------------+


+------------+
; Hierarchy  ;
+------------+
fir_top
 |-- fir_top_st:fir_top_st_component
      |-- sadd:Uaddl_0_n_0_n
      |-- sadd:Uaddl_0_n_1_n
      |-- sadd:Uaddl_1_n_0_n
      |-- mac_tl:Umtl
      |-- ram_lut:Ur0_n
           |-- ram_2pt_var:ram
                |-- altsyncram:altsyncram_component
                     |-- altsyncram_qs41:auto_generated