fir_top.hif

Altera FPGA CPLD设计高级篇电子书籍

Version 4.0 Build 187 1/20/2004 SJ Full Version
32
OFF
OFF
OFF
OFF
OFF
# entity
fir_top
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
fir_top.vhd
1077224605
4
# storage
db|fir_top(0).cnf
db|fir_top(0).cnf
# internal_option {
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
}
# end
# entity
fir_top_st
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
fir_top_st.v
1077224605
7
# storage
db|fir_top(1).cnf
db|fir_top(1).cnf
# internal_option {
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
}
# user_parameter {
DATA_WIDTH
12
PARAMETER_DEC
DEF
COEF_WIDTH
10
PARAMETER_DEC
DEF
ACCUM_WIDTH
27
PARAMETER_DEC
DEF
}
# end
# entity
par_ld_ser_tdl_nc
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
..|..|..|..|..|..|megacore|fir_compiler-v2.7.1|lib|par_ld_ser_tdl_nc.v
1070672878
7
# storage
db|fir_top(2).cnf
db|fir_top(2).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
}
# user_parameter {
WIDTH
13
PARAMETER_DEC
USR
WDLY
11
PARAMETER_DEC
DEF
}
# end
# entity
lc_tdl_strat
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
..|..|..|..|..|..|megacore|fir_compiler-v2.7.1|lib|lc_tdl_strat.v
1070672876
7
# storage
db|fir_top(3).cnf
db|fir_top(3).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
}
# user_parameter {
DEPTH
13
PARAMETER_DEC
USR
DEPTH_ADDR
4
PARAMETER_DEC
USR
WIDTH
13
PARAMETER_DEC
USR
CORE_WIDTH
16
PARAMETER_DEC
USR
}
# end
# entity
sym_add_ser
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
..|..|..|..|..|..|megacore|fir_compiler-v2.7.1|lib|sym_add_ser.v
1070672878
7
# storage
db|fir_top(4).cnf
db|fir_top(4).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
}
# user_parameter {
DATA_WIDTH
1
PARAMETER_DEC
USR
}
# end
# entity
ram_lut
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
..|..|..|..|..|..|megacore|fir_compiler-v2.7.1|lib|ram_lut.v
1070672878
7
# storage
db|fir_top(5).cnf
db|fir_top(5).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
}
# user_parameter {
data_width
13
PARAMETER_DEC
USR
addr_width
8
PARAMETER_DEC
USR
depth
256
PARAMETER_DEC
USR
init_file
fir_top_coef_0.mif
PARAMETER_STRING
USR
mem_core
M4k
PARAMETER_STRING
USR
}
# end
# entity
ram_2pt_var
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
..|..|..|..|..|..|megacore|fir_compiler-v2.7.1|lib|ram_2pt_var.v
1070672878
7
# storage
db|fir_top(6).cnf
db|fir_top(6).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
}
# user_parameter {
DEPTH
256
PARAMETER_DEC
USR
DEPTH_ADDR
8
PARAMETER_DEC
USR
DATA_WIDTH
13
PARAMETER_DEC
USR
INIT_FILE
fir_top_coef_0.mif
PARAMETER_STRING
USR
MEM_CORE
M4k
PARAMETER_STRING
USR
}
# end
# entity
altsyncram
# case_insensitive
# source_file
..|..|..|..|..|..|quartus4_0|libraries|megafunctions|altsyncram.tdf
1074673720
6
# storage
db|fir_top(7).cnf
db|fir_top(7).cnf
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
13
PARAMETER_DEC
USR
WIDTHAD_A
8
PARAMETER_DEC
USR
NUMWORDS_A
256
PARAMETER_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
13
PARAMETER_DEC
USR
WIDTHAD_B
8
PARAMETER_DEC
USR
NUMWORDS_B
256
PARAMETER_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
M4k
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
INIT_FILE
fir_top_coef_0.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Stratix
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_qs41
PARAMETER_UNKNOWN
USR
}
# used_port {
address_a
address_a
address_a
address_a
address_a
address_a
address_a
address_a
address_b
address_b
address_b
address_b
address_b
address_b
address_b
address_b
clock0
clock1
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
wren_a
}
# include_file {
..|..|..|..|..|..|quartus4_0|libraries|megafunctions|stratix_ram_block.inc
1065263632
..|..|..|..|..|..|quartus4_0|libraries|megafunctions|lpm_mux.inc
1065260910
..|..|..|..|..|..|quartus4_0|libraries|megafunctions|lpm_decode.inc
1065260278
..|..|..|..|..|..|quartus4_0|libraries|megafunctions|aglobal.inc
1067303370
..|..|..|..|..|..|quartus4_0|libraries|megafunctions|altsyncram.inc
1067566990
..|..|..|..|..|..|quartus4_0|libraries|megafunctions|a_rdenreg.inc
1065252478
..|..|..|..|..|..|quartus4_0|libraries|megafunctions|altrom.inc
1065256474
..|..|..|..|..|..|quartus4_0|libraries|megafunctions|altram.inc
1065256336
..|..|..|..|..|..|quartus4_0|libraries|megafunctions|altdpram.inc
1065255364
..|..|..|..|..|..|quartus4_0|libraries|megafunctions|altqpram.inc
1065256280
}
# end
# entity
altsyncram_qs41
# case_insensitive
# source_file
db|altsyncram_qs41.tdf
1077224780
6
# storage
db|fir_top(8).cnf
db|fir_top(8).cnf
# used_port {
wren_a
data_a0
data_a1
data_a2
data_a3
data_a4
data_a5
data_a6
data_a7
data_a8
data_a9
data_a10
data_a11
data_a12
address_a0
address_a1
address_a2
address_a3
address_a4
address_a5
address_a6
address_a7
address_b0
address_b1
address_b2
address_b3
address_b4
address_b5
address_b6
address_b7
clock0
clock1
q_b0
q_b1
q_b2
q_b3
q_b4
q_b5
q_b6
q_b7
q_b8
q_b9
q_b10
q_b11
q_b12
}
# memory_file {
fir_top_coef_0.mif
1077224605
}
# end
# entity
ram_lut
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
..|..|..|..|..|..|megacore|fir_compiler-v2.7.1|lib|ram_lut.v
1070672878
7
# storage
db|fir_top(9).cnf
db|fir_top(9).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
}
# user_parameter {
data_width
13
PARAMETER_DEC
USR
addr_width
8
PARAMETER_DEC
USR
depth
256
PARAMETER_DEC
USR
init_file
fir_top_coef_1.mif
PARAMETER_STRING
USR
mem_core
M4k
PARAMETER_STRING
USR
}
# end
# entity
ram_2pt_var
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
..|..|..|..|..|..|megacore|fir_compiler-v2.7.1|lib|ram_2pt_var.v
1070672878
7
# storage
db|fir_top(10).cnf
db|fir_top(10).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
}
# user_parameter {
DEPTH
256
PARAMETER_DEC
USR
DEPTH_ADDR
8
PARAMETER_DEC
USR
DATA_WIDTH
13
PARAMETER_DEC
USR
INIT_FILE
fir_top_coef_1.mif
PARAMETER_STRING
USR
MEM_CORE
M4k
PARAMETER_STRING
USR
}
# end
# entity
altsyncram
# case_insensitive
# source_file
..|..|..|..|..|..|quartus4_0|libraries|megafunctions|altsyncram.tdf
1074673720
6
# storage
db|fir_top(11).cnf
db|fir_top(11).cnf
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
13
PARAMETER_DEC
USR
WIDTHAD_A
8
PARAMETER_DEC
USR
NUMWORDS_A
256
PARAMETER_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
13
PARAMETER_DEC
USR
WIDTHAD_B
8
PARAMETER_DEC
USR
NUMWORDS_B
256
PARAMETER_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF