fir_top.map.qmsg

Altera FPGA CPLD设计高级篇电子书籍

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.0 Build 187 1/20/2004 SJ Full Version " "Info: Version 4.0 Build 187 1/20/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Feb 19 13:06:18 2004 " "Info: Processing started: Thu Feb 19 13:06:18 2004" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off fir_top -c fir_top " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off fir_top -c fir_top" {  } {  } 0}
{ "Info" "ISGN_SEARCH_FILE" "fir_top.vhd 2 1 " "Info: Using design file fir_top.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 fir_top-SYN " "Info: Found design unit 1: fir_top-SYN" {  } { { "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/fir_top.vhd" "fir_top-SYN" "" { Text "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/fir_top.vhd" 55 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 fir_top " "Info: Found entity 1: fir_top" {  } { { "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/fir_top.vhd" "fir_top" "" { Text "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/fir_top.vhd" 42 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_SEARCH_FILE" "fir_top_st.v 1 1 " "Info: Using design file fir_top_st.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 fir_top_st " "Info: Found entity 1: fir_top_st" {  } { { "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/fir_top_st.v" "fir_top_st" "" { Text "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/fir_top_st.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_SEARCH_FILE" "../../../../../../megacore/fir_compiler-v2.7.1/lib/par_ld_ser_tdl_nc.v 1 1 " "Info: Using design file ../../../../../../megacore/fir_compiler-v2.7.1/lib/par_ld_ser_tdl_nc.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 par_ld_ser_tdl_nc " "Info: Found entity 1: par_ld_ser_tdl_nc" {  } { { "c:/megacore/fir_compiler-v2.7.1/lib/par_ld_ser_tdl_nc.v" "par_ld_ser_tdl_nc" "" { Text "c:/megacore/fir_compiler-v2.7.1/lib/par_ld_ser_tdl_nc.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WSGN_SKIP_FILE_CANDID_TOP" "par_ld_ser_tdl_nc " "Warning: Found the following files while searching for definition of entity par_ld_ser_tdl_nc, but did not use these files because already using a different file containing the entity definition" { { "Warning" "WSGN_SKIP_FILE_CANDID_SUB" "../../../../../../megacore/fir_compiler-v2.7.1/lib_time_limited/par_ld_ser_tdl_nc.v " "Warning: File: ../../../../../../megacore/fir_compiler-v2.7.1/lib_time_limited/par_ld_ser_tdl_nc.v" {  } {  } 0}  } {  } 0}
{ "Info" "ISGN_SEARCH_FILE" "../../../../../../megacore/fir_compiler-v2.7.1/lib/lc_tdl_strat.v 1 1 " "Info: Using design file ../../../../../../megacore/fir_compiler-v2.7.1/lib/lc_tdl_strat.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 lc_tdl_strat " "Info: Found entity 1: lc_tdl_strat" {  } { { "c:/megacore/fir_compiler-v2.7.1/lib/lc_tdl_strat.v" "lc_tdl_strat" "" { Text "c:/megacore/fir_compiler-v2.7.1/lib/lc_tdl_strat.v" 12 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WSGN_SKIP_FILE_CANDID_TOP" "lc_tdl_strat " "Warning: Found the following files while searching for definition of entity lc_tdl_strat, but did not use these files because already using a different file containing the entity definition" { { "Warning" "WSGN_SKIP_FILE_CANDID_SUB" "../../../../../../megacore/fir_compiler-v2.7.1/lib_time_limited/lc_tdl_strat.v " "Warning: File: ../../../../../../megacore/fir_compiler-v2.7.1/lib_time_limited/lc_tdl_strat.v" {  } {  } 0}  } {  } 0}
{ "Info" "ISGN_SEARCH_FILE" "../../../../../../megacore/fir_compiler-v2.7.1/lib/sym_add_ser.v 1 1 " "Info: Using design file ../../../../../../megacore/fir_compiler-v2.7.1/lib/sym_add_ser.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 sym_add_ser " "Info: Found entity 1: sym_add_ser" {  } { { "c:/megacore/fir_compiler-v2.7.1/lib/sym_add_ser.v" "sym_add_ser" "" { Text "c:/megacore/fir_compiler-v2.7.1/lib/sym_add_ser.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WSGN_SKIP_FILE_CANDID_TOP" "sym_add_ser " "Warning: Found the following files while searching for definition of entity sym_add_ser, but did not use these files because already using a different file containing the entity definition" { { "Warning" "WSGN_SKIP_FILE_CANDID_SUB" "../../../../../../megacore/fir_compiler-v2.7.1/lib_time_limited/sym_add_ser.v " "Warning: File: ../../../../../../megacore/fir_compiler-v2.7.1/lib_time_limited/sym_add_ser.v" {  } {  } 0}  } {  } 0}
{ "Info" "ISGN_SEARCH_FILE" "../../../../../../megacore/fir_compiler-v2.7.1/lib/ram_lut.v 1 1 " "Info: Using design file ../../../../../../megacore/fir_compiler-v2.7.1/lib/ram_lut.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 ram_lut " "Info: Found entity 1: ram_lut" {  } { { "c:/megacore/fir_compiler-v2.7.1/lib/ram_lut.v" "ram_lut" "" { Text "c:/megacore/fir_compiler-v2.7.1/lib/ram_lut.v" 37 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WSGN_SKIP_FILE_CANDID_TOP" "ram_lut " "Warning: Found the following files while searching for definition of entity ram_lut, but did not use these files because already using a different file containing the entity definition" { { "Warning" "WSGN_SKIP_FILE_CANDID_SUB" "../../../../../../megacore/fir_compiler-v2.7.1/lib_time_limited/ram_lut.v " "Warning: File: ../../../../../../megacore/fir_compiler-v2.7.1/lib_time_limited/ram_lut.v" {  } {  } 0}  } {  } 0}
{ "Info" "ISGN_SEARCH_FILE" "../../../../../../megacore/fir_compiler-v2.7.1/lib/ram_2pt_var.v 1 1 " "Info: Using design file ../../../../../../megacore/fir_compiler-v2.7.1/lib/ram_2pt_var.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 ram_2pt_var " "Info: Found entity 1: ram_2pt_var" {  } { { "c:/megacore/fir_compiler-v2.7.1/lib/ram_2pt_var.v" "ram_2pt_var" "" { Text "c:/megacore/fir_compiler-v2.7.1/lib/ram_2pt_var.v" 37 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WSGN_SKIP_FILE_CANDID_TOP" "ram_2pt_var " "Warning: Found the following files while searching for definition of entity ram_2pt_var, but did not use these files because already using a different file containing the entity definition" { { "Warning" "WSGN_SKIP_FILE_CANDID_SUB" "../../../../../../megacore/fir_compiler-v2.7.1/lib_time_limited/ram_2pt_var.v " "Warning: File: ../../../../../../megacore/fir_compiler-v2.7.1/lib_time_limited/ram_2pt_var.v" {  } {  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../../../../quartus4_0/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units and 1 entities in source file ../../../../../../quartus4_0/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "c:/quartus4_0/libraries/megafunctions/altsyncram.tdf" "altsyncram" "" { Text "c:/quartus4_0/libraries/megafunctions/altsyncram.tdf" 430 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_qs41.tdf 1 1 " "Info: Found 1 design units and 1 entities in source file db/altsyncram_qs41.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_qs41 " "Info: Found entity 1: altsyncram_qs41" {  } { { "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/altsyncram_qs41.tdf" "altsyncram_qs41" "" { Text "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/altsyncram_qs41.tdf" 31 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_rs41.tdf 1 1 " "Info: Found 1 design units and 1 entities in source file db/altsyncram_rs41.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_rs41 " "Info: Found entity 1: altsyncram_rs41" {  } { { "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/altsyncram_rs41.tdf" "altsyncram_rs41" "" { Text "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/altsyncram_rs41.tdf" 31 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_6m41.tdf 1 1 " "Info: Found 1 design units and 1 entities in source file db/altsyncram_6m41.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_6m41 " "Info: Found entity 1: altsyncram_6m41" {  } { { "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/altsyncram_6m41.tdf" "altsyncram_6m41" "" { Text "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/db/altsyncram_6m41.tdf" 31 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_SEARCH_FILE" "../../../../../../megacore/fir_compiler-v2.7.1/lib/sadd.v 1 1 " "Info: Using design file ../../../../../../megacore/fir_compiler-v2.7.1/lib/sadd.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 sadd " "Info: Found entity 1: sadd" {  } { { "c:/megacore/fir_compiler-v2.7.1/lib/sadd.v" "sadd" "" { Text "c:/megacore/fir_compiler-v2.7.1/lib/sadd.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WSGN_SKIP_FILE_CANDID_TOP" "sadd " "Warning: Found the following files while searching for definition of entity sadd, but did not use these files because already using a different file containing the entity definition" { { "Warning" "WSGN_SKIP_FILE_CANDID_SUB" "../../../../../../megacore/fir_compiler-v2.7.1/lib_time_limited/sadd.v " "Warning: File: ../../../../../../megacore/fir_compiler-v2.7.1/lib_time_limited/sadd.v" {  } {  } 0}  } {  } 0}
{ "Info" "ISGN_SEARCH_FILE" "../../../../../../megacore/fir_compiler-v2.7.1/lib/mac_tl.v 1 1 " "Info: Using design file ../../../../../../megacore/fir_compiler-v2.7.1/lib/mac_tl.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 mac_tl " "Info: Found entity 1: mac_tl" {  } { { "c:/megacore/fir_compiler-v2.7.1/lib/mac_tl.v" "mac_tl" "" { Text "c:/megacore/fir_compiler-v2.7.1/lib/mac_tl.v" 1 -1 0 } }  } 0}  } {  } 0}