fir_top.tan.summary

Altera FPGA CPLD设计高级篇电子书籍

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 2.507 ns
From           : data_in[4]
To             : fir_top_st:fir_top_st_component|par_ld_ser_tdl_nc:Utdl_0_a|data_reg[4]

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 8.052 ns
From           : fir_top_st:fir_top_st_component|ser_ctrl_nc:Usc|tdl_wait[12]
To             : rdy_to_ld

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -2.021 ns
From           : data_in[9]
To             : fir_top_st:fir_top_st_component|par_ld_ser_tdl_nc:Utdl_0_a|data_reg[9]

Type           : Worst-case minimum tco
Slack          : N/A
Required Time  : None
Actual Time    : 6.881 ns
From           : fir_top_st:fir_top_st_component|scale_shft_comb:Usscx|res[24]~reg0
To             : fir_result[24]

Type           : Clock Setup: 'clock'
Slack          : N/A
Required Time  : None
Actual Time    : 255.56 MHz ( period = 3.913 ns )
From           : fir_top_st:fir_top_st_component|ram_lut:Ur2_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_6m41:auto_generated|ram_block1a0~porta_datain_reg0
To             : fir_top_st:fir_top_st_component|ram_lut:Ur2_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_6m41:auto_generated|ram_block1a0~porta_memory_reg0

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