fir_top_st_model.vhd

Altera FPGA CPLD设计高级篇电子书籍

LIBRARY ieee;                              
USE ieee.std_logic_1164.all;               
USE ieee.std_logic_arith.all; 
USE ieee.std_logic_unsigned.all;
library leaf_lib;
USE leaf_lib.LEAF_NODES_PACK.all;

entity fir_top_st is 
generic(
	DATA_WIDTH : integer :=12;
	COEF_WIDTH : integer :=10;
	ACCUM_WIDTH : integer :=27
	);
port(
	clk: in std_logic;
	 rst: in std_logic;
	 data_in: in std_logic_vector (DATA_WIDTH-1 downto 0);
	rdy_to_ld: out std_logic;
	done: out std_logic;
	fir_result: out std_logic_vector (ACCUM_WIDTH-1 downto 0)
	);
end fir_top_st;
architecture only of fir_top_st is 
	 signal vcc : std_logic;
	 signal gnd : std_logic;
	 signal rdy_int: std_logic;
	 signal done_int: std_logic;
	 signal tdl_ld: std_logic;
	 signal sa_rst: std_logic;
	 signal sa_inv: std_logic;
	 signal pre_rdy: std_logic;
	 signal addr_low: std_logic;
	 signal clk_en: std_logic;
	 signal ser_eab_0_n: std_logic;
	 signal ser_eab_1_n: std_logic;
	 signal ser_eab_2_n: std_logic;
	 signal ser_eab_3_n: std_logic;
	 signal data_ee: std_logic_vector (DATA_WIDTH  downto  0);
	 signal ser_dat_0_n: std_logic;
	 signal ld_s2p: std_logic;
	 signal ser_dat_1_n: std_logic;
	 signal ser_dat_2_n: std_logic;
	 signal ser_dat_3_n: std_logic;
	 signal ser_dat_4_n: std_logic;
	 signal ser_dat_5_n: std_logic;
	 signal ser_dat_6_n: std_logic;
	 signal ser_dat_7_n: std_logic;
	 signal ser_dat_8_n: std_logic;
	 signal ser_dat_9_n: std_logic;
	 signal ser_dat_10_n: std_logic;
	 signal ser_dat_11_n: std_logic;
	 signal ser_dat_12_n: std_logic;
	 signal ser_dat_13_n: std_logic;
	 signal ser_dat_14_n: std_logic;
	 signal ser_dat_15_n: std_logic;
	 signal ser_dat_16_n: std_logic;
	 signal tdl_data_0_n: std_logic_vector (15 downto 0);
	 signal ser_dat_17_n: std_logic;
	 signal ser_dat_18_n: std_logic;
	 signal ser_dat_19_n: std_logic;
	 signal ser_dat_20_n: std_logic;
	 signal ser_dat_21_n: std_logic;
	 signal ser_dat_22_n: std_logic;
	 signal ser_dat_23_n: std_logic;
	 signal ser_dat_24_n: std_logic;
	 signal ser_dat_25_n: std_logic;
	 signal ser_dat_26_n: std_logic;
	 signal ser_dat_27_n: std_logic;
	 signal ser_dat_28_n: std_logic;
	 signal ser_dat_29_n: std_logic;
	 signal ser_dat_30_n: std_logic;
	 signal ser_dat_31_n: std_logic;
	 signal ser_dat_32_n: std_logic;
	 signal tdl_data_1_n: std_logic_vector (15 downto 0);
	 signal ser_dat_33_n: std_logic;
	 signal ser_dat_34_n: std_logic;
	 signal ser_dat_35_n: std_logic;
	 signal ser_dat_36_n: std_logic;
	 signal tdl_data_2_n: std_logic_vector (15 downto 0);
	 signal  lut_val_0_n: std_logic_vector (12 downto 0);
	 signal  lut_val_1_n: std_logic_vector (12 downto 0);
	 signal  lut_val_2_n: std_logic_vector (12 downto 0);
	 signal  tree_l_0_n_0_n: std_logic_vector (13 downto 0);
	 signal  tree_l_0_n_1_n: std_logic_vector (13 downto 0);
	 signal  tree_l_1_n_0_n: std_logic_vector (14 downto 0);
	 signal  mac_res: std_logic_vector (14 downto 0);
	 signal  atree_res: std_logic_vector (14 downto 0);
	 signal  shft: std_logic_vector (11 downto 0);
	 signal  accum: std_logic_vector (15 downto 0);
	 signal  fir_int_res: std_logic_vector (27 downto 0);

begin
		gnd <= '0';
		vcc <= '1';
	addr_low  <='0';
	clk_en  <='1';
	data_ee  <=  data_in(DATA_WIDTH -1)&data_in;
	lut_val_2_n(12)  <= lut_val_2_n(11);
	mac_res <=tree_l_1_n_0_n;
	fir_result  <= fir_int_res(ACCUM_WIDTH-1 downto 0);
	done  <= done_int;
	rdy_to_ld  <= rdy_int;

	Utdl_0_a : par_ld_ser_tdl_nc
	GENERIC MAP( WIDTH  => 13)
	PORT MAP (clk =>clk,
		clk_en =>vcc,
		data_in =>data_ee,
		tdl_ld =>pre_rdy,
		data_out =>ser_eab_0_n);

	Utdl_0_n  : lc_tdl_strat
	GENERIC MAP( CORE_WIDTH  => 16,
		DEPTH  => 13,
		DEPTH_ADDR  => 4,
		WIDTH  => 13)
	PORT MAP (clk =>clk,
		rst =>tdl_ld,
		data_in =>ser_eab_0_n,
		data_out =>tdl_data_0_n,
		ntdl =>ser_eab_1_n);

	Utdl_1_n  : lc_tdl_strat
	GENERIC MAP( CORE_WIDTH  => 16,
		DEPTH  => 13,
		DEPTH_ADDR  => 4,
		WIDTH  => 13)
	PORT MAP (clk =>clk,
		rst =>tdl_ld,
		data_in =>ser_eab_1_n,
		data_out =>tdl_data_1_n,
		ntdl =>ser_eab_2_n);

	Utdl_2_n  : lc_tdl_strat
	GENERIC MAP( CORE_WIDTH  => 16,
		DEPTH  => 13,
		DEPTH_ADDR  => 4,
		WIDTH  => 13)
	PORT MAP (clk =>clk,
		rst =>tdl_ld,
		data_in =>ser_eab_2_n,
		data_out =>tdl_data_2_n,
		ntdl =>ser_eab_3_n);

	sym_0_n : sym_add_ser
	GENERIC MAP( DATA_WIDTH  => 1)
	PORT MAP (rst =>rdy_int,
		clk =>clk,
		a_in =>ser_eab_0_n,
		b_in =>tdl_data_2_n(3),
		data_out =>ser_dat_0_n);

	sym_1_n : sym_add_ser
	GENERIC MAP( DATA_WIDTH  => 1)
	PORT MAP (rst =>rdy_int,
		clk =>clk,
		a_in =>tdl_data_0_n(0),
		b_in =>tdl_data_2_n(2),
		data_out =>ser_dat_1_n);

	sym_2_n : sym_add_ser
	GENERIC MAP( DATA_WIDTH  => 1)
	PORT MAP (rst =>rdy_int,
		clk =>clk,
		a_in =>tdl_data_0_n(1),
		b_in =>tdl_data_2_n(1),
		data_out =>ser_dat_2_n);

	sym_3_n : sym_add_ser
	GENERIC MAP( DATA_WIDTH  => 1)
	PORT MAP (rst =>rdy_int,
		clk =>clk,
		a_in =>tdl_data_0_n(2),
		b_in =>tdl_data_2_n(0),
		data_out =>ser_dat_3_n);

	sym_4_n : sym_add_ser
	GENERIC MAP( DATA_WIDTH  => 1)
	PORT MAP (rst =>rdy_int,
		clk =>clk,
		a_in =>tdl_data_0_n(3),
		b_in =>tdl_data_1_n(15),
		data_out =>ser_dat_4_n);

	sym_5_n : sym_add_ser
	GENERIC MAP( DATA_WIDTH  => 1)
	PORT MAP (rst =>rdy_int,
		clk =>clk,
		a_in =>tdl_data_0_n(4),
		b_in =>tdl_data_1_n(14),
		data_out =>ser_dat_5_n);

	sym_6_n : sym_add_ser
	GENERIC MAP( DATA_WIDTH  => 1)
	PORT MAP (rst =>rdy_int,
		clk =>clk,
		a_in =>tdl_data_0_n(5),
		b_in =>tdl_data_1_n(13),
		data_out =>ser_dat_6_n);

	sym_7_n : sym_add_ser
	GENERIC MAP( DATA_WIDTH  => 1)
	PORT MAP (rst =>rdy_int,
		clk =>clk,
		a_in =>tdl_data_0_n(6),
		b_in =>tdl_data_1_n(12),
		data_out =>ser_dat_7_n);

	sym_8_n : sym_add_ser
	GENERIC MAP( DATA_WIDTH  => 1)
	PORT MAP (rst =>rdy_int,
		clk =>clk,
		a_in =>tdl_data_0_n(7),
		b_in =>tdl_data_1_n(11),
		data_out =>ser_dat_8_n);

	sym_9_n : sym_add_ser
	GENERIC MAP( DATA_WIDTH  => 1)
	PORT MAP (rst =>rdy_int,
		clk =>clk,
		a_in =>tdl_data_0_n(8),
		b_in =>tdl_data_1_n(10),
		data_out =>ser_dat_9_n);

	sym_10_n : sym_add_ser
	GENERIC MAP( DATA_WIDTH  => 1)
	PORT MAP (rst =>rdy_int,
		clk =>clk,
		a_in =>tdl_data_0_n(9),
		b_in =>tdl_data_1_n(9),
		data_out =>ser_dat_10_n);

	sym_11_n : sym_add_ser
	GENERIC MAP( DATA_WIDTH  => 1)
	PORT MAP (rst =>rdy_int,
		clk =>clk,
		a_in =>tdl_data_0_n(10),
		b_in =>tdl_data_1_n(8),
		data_out =>ser_dat_11_n);

	sym_12_n : sym_add_ser
	GENERIC MAP( DATA_WIDTH  => 1)
	PORT MAP (rst =>rdy_int,
		clk =>clk,
		a_in =>tdl_data_0_n(11),
		b_in =>tdl_data_1_n(7),
		data_out =>ser_dat_12_n);

	sym_13_n : sym_add_ser
	GENERIC MAP( DATA_WIDTH  => 1)
	PORT MAP (rst =>rdy_int,
		clk =>clk,
		a_in =>tdl_data_0_n(12),
		b_in =>tdl_data_1_n(6),
		data_out =>ser_dat_13_n);

	sym_14_n : sym_add_ser
	GENERIC MAP( DATA_WIDTH  => 1)
	PORT MAP (rst =>rdy_int,
		clk =>clk,
		a_in =>tdl_data_0_n(13),
		b_in =>tdl_data_1_n(5),
		data_out =>ser_dat_14_n);

	sym_15_n : sym_add_ser
	GENERIC MAP( DATA_WIDTH  => 1)
	PORT MAP (rst =>rdy_int,
		clk =>clk,
		a_in =>tdl_data_0_n(14),
		b_in =>tdl_data_1_n(4),
		data_out =>ser_dat_15_n);

	sym_16_n : sym_add_ser
	GENERIC MAP( DATA_WIDTH  => 1)
	PORT MAP (rst =>rdy_int,
		clk =>clk,
		a_in =>tdl_data_0_n(15),
		b_in =>tdl_data_1_n(3),
		data_out =>ser_dat_16_n);

	sym_17_n : sym_add_ser
	GENERIC MAP( DATA_WIDTH  => 1)
	PORT MAP (rst =>rdy_int,
		clk =>clk,
		a_in =>tdl_data_1_n(0),
		b_in =>tdl_data_1_n(2),
		data_out =>ser_dat_17_n);

	sym_18_n : sym_add_ser
	GENERIC MAP( DATA_WIDTH  => 1)
	PORT MAP (clk =>clk,
		rst =>rdy_int,
		a_in =>tdl_data_1_n(1),
		b_in =>gnd,
		data_out =>ser_dat_18_n);

	Ur0_n : ram_lut
	GENERIC MAP( init_file  => "fir_top_coef_0.hex",
		data_width  => 13,
		addr_width  => 8,
		depth  => 256,
		mem_core  => "M4k")
	PORT MAP (clk_in =>clk,
		clk_out =>clk,
		addr_in(7) =>ser_dat_7_n,
		addr_in(6) =>ser_dat_6_n,
		addr_in(5) =>ser_dat_5_n,
		addr_in(4) =>ser_dat_4_n,
		addr_in(3) =>ser_dat_3_n,
		addr_in(2) =>ser_dat_2_n,
		addr_in(1) =>ser_dat_1_n,
		addr_in(0) =>ser_dat_0_n,
		wr_en =>gnd,
		data_out => lut_val_0_n(12 downto 0));

	Ur1_n : ram_lut
	GENERIC MAP( init_file  => "fir_top_coef_1.hex",
		data_width  => 13,
		addr_width  => 8,
		depth  => 256,
		mem_core  => "M4k")
	PORT MAP (clk_in =>clk,
		clk_out =>clk,
		addr_in(7) =>ser_dat_15_n,
		addr_in(6) =>ser_dat_14_n,
		addr_in(5) =>ser_dat_13_n,
		addr_in(4) =>ser_dat_12_n,
		addr_in(3) =>ser_dat_11_n,
		addr_in(2) =>ser_dat_10_n,
		addr_in(1) =>ser_dat_9_n,
		addr_in(0) =>ser_dat_8_n,
		wr_en =>gnd,
		data_out => lut_val_1_n(12 downto 0));

	Ur2_n : ram_lut
	GENERIC MAP( init_file  => "fir_top_coef_2.hex",
		data_width  => 12,
		addr_width  => 3,
		depth  => 8,
		mem_core  => "M4k")
	PORT MAP (clk_in =>clk,
		clk_out =>clk,
		addr_in(2) =>ser_dat_18_n,
		addr_in(1) =>ser_dat_17_n,
		addr_in(0) =>ser_dat_16_n,
		wr_en =>gnd,
		data_out => lut_val_2_n(11 downto 0));

	Uaddl_0_n_0_n  : sadd
	GENERIC MAP( IN_WIDTH  => 13,
		PIPE_DEPTH  => 1)
	PORT MAP (clk =>clk,
		ain =>lut_val_0_n,
		bin =>lut_val_1_n,
		res =>tree_l_0_n_0_n);

	Uaddl_0_n_1_n  : sadd
	GENERIC MAP( IN_WIDTH  => 13,
		PIPE_DEPTH  => 1)
	PORT MAP (clk =>clk,
		ain =>lut_val_2_n,
		bin(0) =>gnd,
		bin(1) =>gnd,
		bin(2) =>gnd,
		bin(3) =>gnd,
		bin(4) =>gnd,
		bin(5) =>gnd,
		bin(6) =>gnd,
		bin(7) =>gnd,
		bin(8) =>gnd,
		bin(9) =>gnd,
		bin(10) =>gnd,
		bin(11) =>gnd,
		bin(12) =>gnd,
		res =>tree_l_0_n_1_n);

	Uaddl_1_n_0_n  : sadd
	GENERIC MAP( IN_WIDTH  => 14,
		PIPE_DEPTH  => 1)
	PORT MAP (clk =>clk,
		ain =>tree_l_0_n_0_n,
		bin =>tree_l_0_n_1_n,
		res =>tree_l_1_n_0_n);

	Umtl  : mac_tl
	GENERIC MAP( DATA_WIDTH  => 15)
	PORT MAP (clk =>clk,
		data_in =>mac_res,
		data_out =>atree_res);

	Usa  : scale_accum
	GENERIC MAP( WIDTH_A  => 15)
	PORT MAP (clk =>clk,
		rst =>sa_rst,
		inv =>sa_inv,
		ain =>atree_res,
		accum_out =>accum);

	Usershft : ser_shft
	GENERIC MAP( SHIFT_WIDTH  => 12)
	PORT MAP (clk =>clk,
		rst =>gnd,
		ain =>accum(0),
		shft_out =>shft);

	Usscx  : scale_shft_comb
	GENERIC MAP( WIDTH_ACCM  => 16,
		WIDTH_SHFT  => 12,
		WIDTH_RES  => 28)
	PORT MAP (clk =>clk,
		ce =>done_int,
		accum =>accum,
		shft =>shft,
		res =>fir_int_res);

	Usc  : ser_ctrl_nc
	GENERIC MAP( REG_LEN  =>13,
		PIPE_DLY  =>7,
		RST_DLY  =>6,
		INV_DLY  =>7,
		DONE_DLY  =>5)
	PORT MAP (rst =>rst,
		clk =>clk,
		clk_en =>clk_en,
		pre_rdy =>pre_rdy,
		sa_rst_out =>sa_rst,
		ser_inv_out =>sa_inv,
		rdy_to_ld =>rdy_int,
		tdl_ld =>tdl_ld,
		done =>done_int);


end;