fir_top.qsf

Altera FPGA CPLD设计高级篇电子书籍

# Copyright (C) 1991-2004 Altera Corporation
# Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
# support information,  device programming or simulation file,  and any other
# associated  documentation or information  provided by  Altera  or a partner
# under  Altera's   Megafunction   Partnership   Program  may  be  used  only
# to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
# other  use  of such  megafunction  design,  netlist,  support  information,
# device programming or simulation file,  or any other  related documentation
# or information  is prohibited  for  any  other purpose,  including, but not
# limited to  modification,  reverse engineering,  de-compiling, or use  with
# any other  silicon devices,  unless such use is  explicitly  licensed under
# a separate agreement with  Altera  or a megafunction partner.  Title to the
# intellectual property,  including patents,  copyrights,  trademarks,  trade
# secrets,  or maskworks,  embodied in any such megafunction design, netlist,
# support  information,  device programming or simulation file,  or any other
# related documentation or information provided by  Altera  or a megafunction
# partner, remains with Altera, the megafunction partner, or their respective
# licensors. No other licenses, including any licenses needed under any third
# party's intellectual property, are provided herein.


# The default values for assignments are stored in the file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 4.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:05:12  FEBRUARY 19, 2004"
set_global_assignment -name LAST_QUARTUS_VERSION 4.0

# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name FAMILY Stratix
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE FASTEST
set_global_assignment -name TOP_LEVEL_ENTITY fir_top
set_global_assignment -name USER_LIBRARIES "c:\\megacore\\fir_compiler-v2.7.1\\lib/;c:\\megacore\\fir_compiler-v2.7.1\\lib_time_limited/"

# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EP1S10B672C6

# LogicLock Region Assignments
# ============================
set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT ON
set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_FILE atom_netlists/fir_top.vqm

# ---------------------
# start ENTITY(fir_top)


	# --------------------------------
	# start LOGICLOCK_REGION(fir_lock)

		# LogicLock Region Assignments
		# ============================
		set_global_assignment -name LL_ORIGIN X3_Y1 -section_id fir_lock
		set_global_assignment -name LL_HEIGHT 8 -section_id fir_lock
		set_global_assignment -name LL_WIDTH 13 -section_id fir_lock
		set_global_assignment -name LL_STATE LOCKED -section_id fir_lock
		set_global_assignment -name LL_AUTO_SIZE OFF -section_id fir_lock
		set_global_assignment -name LL_RESERVED OFF -section_id fir_lock
		set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id fir_lock
		set_global_assignment -name LL_SOFT OFF -section_id fir_lock
		set_global_assignment -name LL_MEMBER_OF fir_lock -section_id fir_lock
		set_instance_assignment -name LL_NODE_LOCATION LAB_X12_Y2 -to "fir_top_st:fir_top_st_component\|lc_tdl_strat:Utdl_0_n\|sft15_n\[11\]" -section_id fir_lock
		set_instance_assignment -name LL_NODE_LOCATION LAB_X12_Y1 -to "fir_top_st:fir_top_st_component\|lc_tdl_strat:Utdl_0_n\|sft15_n\[10\]" -section_id fir_lock
		set_instance_assignment -name LL_NODE_LOCATION LAB_X7_Y1 -to "fir_top_st:fir_top_st_component\|lc_tdl_strat:Utdl_0_n\|sft15_n\[9\]" -section_id fir_lock
		set_instance_assignment -name LL_NODE_LOCATION LAB_X7_Y1 -to "fir_top_st:fir_top_st_component\|lc_tdl_strat:Utdl_0_n\|sft15_n\[8\]" -section_id fir_lock
		set_instance_assignment -name LL_NODE_LOCATION LAB_X5_Y1 -to "fir_top_st:fir_top_st_component\|lc_tdl_strat:Utdl_0_n\|sft15_n\[7\]" -section_id fir_lock
		set_instance_assignment -name LL_NODE_LOCATION LAB_X7_Y1 -to "fir_top_st:fir_top_st_component\|lc_tdl_strat:Utdl_0_n\|sft15_n\[6\]" -section_id fir_lock
		set_instance_assignment -name LL_NODE_LOCATION LAB_X7_Y1 -to "fir_top_st:fir_top_st_component\|lc_tdl_strat:Utdl_0_n\|sft15_n\[5\]" -section_id fir_lock
		set_instance_assignment -name LL_NODE_LOCATION LAB_X7_Y1 -to "fir_top_st:fir_top_st_component\|lc_tdl_strat:Utdl_0_n\|sft15_n\[4\]" -section_id fir_lock
		set_instance_assignment -name LL_NODE_LOCATION LAB_X7_Y1 -to "fir_top_st:fir_top_st_component\|lc_tdl_strat:Utdl_0_n\|sft15_n\[3\]" -section_id fir_lock
		set_instance_assignment -name LL_NODE_LOCATION LAB_X7_Y1 -to "fir_top_st:fir_top_st_component\|lc_tdl_strat:Utdl_0_n\|sft15_n\[2\]" -section_id fir_lock
		set_instance_assignment -name LL_NODE_LOCATION LAB_X7_Y1 -to "fir_top_st:fir_top_st_component\|lc_tdl_strat:Utdl_0_n\|sft15_n\[1\]" -section_id fir_lock