fir_top_st_model.v

Altera FPGA CPLD设计高级篇电子书籍

module fir_top_st (clk, 
              rst, 
              data_in, 
              rdy_to_ld, 
              done, 
              fir_result); 
parameter DATA_WIDTH  = 12;
parameter COEF_WIDTH  = 10;
parameter ACCUM_WIDTH = 27;

input clk, rst;
input [DATA_WIDTH-1:0] data_in;
output rdy_to_ld;
wire rdy_to_ld;
wire rdy_int;
output done;
wire done;
wire done_int;
output [ACCUM_WIDTH-1:0] fir_result;
wire tdl_ld;
wire sa_rst;
wire sa_inv;
wire pre_rdy;
wire addr_low;
assign addr_low = 1'b0;
wire clk_en;
assign clk_en = 1'b1;
wire ser_eab_0_n;
wire ser_eab_1_n;
wire ser_eab_2_n;
wire ser_eab_3_n;
wire [DATA_WIDTH : 0]data_ee;
assign data_ee = {data_in[DATA_WIDTH -1],data_in}; 
wire ser_dat_0_n;
wire ld_s2p;
par_ld_ser_tdl_nc Utdl_0_a(.clk(clk), .clk_en(1'b1),.data_in(data_ee), .tdl_ld(pre_rdy),.data_out(ser_eab_0_n) );
defparam Utdl_0_a.WIDTH = 13;
wire ser_dat_1_n;
wire ser_dat_2_n;
wire ser_dat_3_n;
wire ser_dat_4_n;
wire ser_dat_5_n;
wire ser_dat_6_n;
wire ser_dat_7_n;
wire ser_dat_8_n;
wire ser_dat_9_n;
wire ser_dat_10_n;
wire ser_dat_11_n;
wire ser_dat_12_n;
wire ser_dat_13_n;
wire ser_dat_14_n;
wire ser_dat_15_n;
wire ser_dat_16_n;
wire [15:0]tdl_data_0_n;
lc_tdl_strat Utdl_0_n (
  .clk(clk),
  .rst(tdl_ld),
  .data_in(ser_eab_0_n),
  .data_out(tdl_data_0_n),
  .ntdl(ser_eab_1_n) 
);
defparam Utdl_0_n.CORE_WIDTH = 16;
defparam Utdl_0_n.DEPTH = 13;
defparam Utdl_0_n.DEPTH_ADDR = 4;
defparam Utdl_0_n.WIDTH = 13;
wire ser_dat_17_n;
wire ser_dat_18_n;
wire ser_dat_19_n;
wire ser_dat_20_n;
wire ser_dat_21_n;
wire ser_dat_22_n;
wire ser_dat_23_n;
wire ser_dat_24_n;
wire ser_dat_25_n;
wire ser_dat_26_n;
wire ser_dat_27_n;
wire ser_dat_28_n;
wire ser_dat_29_n;
wire ser_dat_30_n;
wire ser_dat_31_n;
wire ser_dat_32_n;
wire [15:0]tdl_data_1_n;
lc_tdl_strat Utdl_1_n (
  .clk(clk),
  .rst(tdl_ld),
  .data_in(ser_eab_1_n),
  .data_out(tdl_data_1_n),
  .ntdl(ser_eab_2_n) 
);
defparam Utdl_1_n.CORE_WIDTH = 16;
defparam Utdl_1_n.DEPTH = 13;
defparam Utdl_1_n.DEPTH_ADDR = 4;
defparam Utdl_1_n.WIDTH = 13;
wire ser_dat_33_n;
wire ser_dat_34_n;
wire ser_dat_35_n;
wire ser_dat_36_n;
wire [15:0]tdl_data_2_n;
lc_tdl_strat Utdl_2_n (
  .clk(clk),
  .rst(tdl_ld),
  .data_in(ser_eab_2_n),
  .data_out(tdl_data_2_n),
  .ntdl(ser_eab_3_n) 
);
defparam Utdl_2_n.CORE_WIDTH = 16;
defparam Utdl_2_n.DEPTH = 13;
defparam Utdl_2_n.DEPTH_ADDR = 4;
defparam Utdl_2_n.WIDTH = 13;
sym_add_ser sym_0_n(.rst(rdy_int), .clk(clk),.a_in(ser_eab_0_n),.b_in(tdl_data_2_n[3]),.data_out(ser_dat_0_n));
defparam sym_0_n.DATA_WIDTH = 1;
sym_add_ser sym_1_n(.rst(rdy_int), .clk(clk),.a_in(tdl_data_0_n[0]),.b_in(tdl_data_2_n[2]),.data_out(ser_dat_1_n));
defparam sym_1_n.DATA_WIDTH = 1;
sym_add_ser sym_2_n(.rst(rdy_int), .clk(clk),.a_in(tdl_data_0_n[1]),.b_in(tdl_data_2_n[1]),.data_out(ser_dat_2_n));
defparam sym_2_n.DATA_WIDTH = 1;
sym_add_ser sym_3_n(.rst(rdy_int), .clk(clk),.a_in(tdl_data_0_n[2]),.b_in(tdl_data_2_n[0]),.data_out(ser_dat_3_n));
defparam sym_3_n.DATA_WIDTH = 1;
sym_add_ser sym_4_n(.rst(rdy_int), .clk(clk),.a_in(tdl_data_0_n[3]),.b_in(tdl_data_1_n[15]),.data_out(ser_dat_4_n));
defparam sym_4_n.DATA_WIDTH = 1;
sym_add_ser sym_5_n(.rst(rdy_int), .clk(clk),.a_in(tdl_data_0_n[4]),.b_in(tdl_data_1_n[14]),.data_out(ser_dat_5_n));
defparam sym_5_n.DATA_WIDTH = 1;
sym_add_ser sym_6_n(.rst(rdy_int), .clk(clk),.a_in(tdl_data_0_n[5]),.b_in(tdl_data_1_n[13]),.data_out(ser_dat_6_n));
defparam sym_6_n.DATA_WIDTH = 1;
sym_add_ser sym_7_n(.rst(rdy_int), .clk(clk),.a_in(tdl_data_0_n[6]),.b_in(tdl_data_1_n[12]),.data_out(ser_dat_7_n));
defparam sym_7_n.DATA_WIDTH = 1;
sym_add_ser sym_8_n(.rst(rdy_int), .clk(clk),.a_in(tdl_data_0_n[7]),.b_in(tdl_data_1_n[11]),.data_out(ser_dat_8_n));
defparam sym_8_n.DATA_WIDTH = 1;
sym_add_ser sym_9_n(.rst(rdy_int), .clk(clk),.a_in(tdl_data_0_n[8]),.b_in(tdl_data_1_n[10]),.data_out(ser_dat_9_n));
defparam sym_9_n.DATA_WIDTH = 1;
sym_add_ser sym_10_n(.rst(rdy_int), .clk(clk),.a_in(tdl_data_0_n[9]),.b_in(tdl_data_1_n[9]),.data_out(ser_dat_10_n));
defparam sym_10_n.DATA_WIDTH = 1;
sym_add_ser sym_11_n(.rst(rdy_int), .clk(clk),.a_in(tdl_data_0_n[10]),.b_in(tdl_data_1_n[8]),.data_out(ser_dat_11_n));
defparam sym_11_n.DATA_WIDTH = 1;
sym_add_ser sym_12_n(.rst(rdy_int), .clk(clk),.a_in(tdl_data_0_n[11]),.b_in(tdl_data_1_n[7]),.data_out(ser_dat_12_n));
defparam sym_12_n.DATA_WIDTH = 1;
sym_add_ser sym_13_n(.rst(rdy_int), .clk(clk),.a_in(tdl_data_0_n[12]),.b_in(tdl_data_1_n[6]),.data_out(ser_dat_13_n));
defparam sym_13_n.DATA_WIDTH = 1;
sym_add_ser sym_14_n(.rst(rdy_int), .clk(clk),.a_in(tdl_data_0_n[13]),.b_in(tdl_data_1_n[5]),.data_out(ser_dat_14_n));
defparam sym_14_n.DATA_WIDTH = 1;
sym_add_ser sym_15_n(.rst(rdy_int), .clk(clk),.a_in(tdl_data_0_n[14]),.b_in(tdl_data_1_n[4]),.data_out(ser_dat_15_n));
defparam sym_15_n.DATA_WIDTH = 1;
sym_add_ser sym_16_n(.rst(rdy_int), .clk(clk),.a_in(tdl_data_0_n[15]),.b_in(tdl_data_1_n[3]),.data_out(ser_dat_16_n));
defparam sym_16_n.DATA_WIDTH = 1;
sym_add_ser sym_17_n(.rst(rdy_int), .clk(clk),.a_in(tdl_data_1_n[0]),.b_in(tdl_data_1_n[2]),.data_out(ser_dat_17_n));
defparam sym_17_n.DATA_WIDTH = 1;
sym_add_ser sym_18_n(.clk(clk), .rst(rdy_int),.a_in(tdl_data_1_n[1]),.b_in(1'b0),.data_out(ser_dat_18_n));
defparam sym_18_n.DATA_WIDTH = 1;
// --- ROM LUTs ---- 
wire [12:0] lut_val_0_n;
ram_lut Ur0_n(.clk_in(clk), .clk_out(clk), .addr_in( {ser_dat_7_n,ser_dat_6_n,ser_dat_5_n,ser_dat_4_n,ser_dat_3_n,ser_dat_2_n,ser_dat_1_n,ser_dat_0_n } ), .wr_en(1'b0),.data_out( lut_val_0_n[12:0]) ) ;
defparam Ur0_n.init_file = "fir_top_coef_0.v";
defparam Ur0_n.data_width = 13;
defparam Ur0_n.addr_width = 8;
defparam Ur0_n.depth = 256;
defparam Ur0_n.mem_core = "M4k";
wire [12:0] lut_val_1_n;
ram_lut Ur1_n(.clk_in(clk), .clk_out(clk), .addr_in( {ser_dat_15_n,ser_dat_14_n,ser_dat_13_n,ser_dat_12_n,ser_dat_11_n,ser_dat_10_n,ser_dat_9_n,ser_dat_8_n } ), .wr_en(1'b0),.data_out( lut_val_1_n[12:0]) ) ;
defparam Ur1_n.init_file = "fir_top_coef_1.v";
defparam Ur1_n.data_width = 13;
defparam Ur1_n.addr_width = 8;
defparam Ur1_n.depth = 256;
defparam Ur1_n.mem_core = "M4k";
wire [12:0] lut_val_2_n;
ram_lut Ur2_n(.clk_in(clk), .clk_out(clk), .addr_in( {ser_dat_18_n,ser_dat_17_n,ser_dat_16_n } ), .wr_en(1'b0),.data_out( lut_val_2_n[11:0]) ) ;
defparam Ur2_n.init_file = "fir_top_coef_2.v";
defparam Ur2_n.data_width = 12;
defparam Ur2_n.addr_width = 3;
defparam Ur2_n.depth = 8;
defparam Ur2_n.mem_core = "M4k";
assign lut_val_2_n[12] = lut_val_2_n[11];
wire [13:0] tree_l_0_n_0_n;
sadd Uaddl_0_n_0_n (.clk(clk), .ain(lut_val_0_n), .bin(lut_val_1_n), .res(tree_l_0_n_0_n) );
defparam Uaddl_0_n_0_n.IN_WIDTH = 13;
defparam Uaddl_0_n_0_n.PIPE_DEPTH = 1;
wire [13:0] tree_l_0_n_1_n;
sadd Uaddl_0_n_1_n (.clk(clk), .ain(lut_val_2_n), .bin(13'd0), .res(tree_l_0_n_1_n) );
defparam Uaddl_0_n_1_n.IN_WIDTH = 13;
defparam Uaddl_0_n_1_n.PIPE_DEPTH = 1;

wire [14:0] tree_l_1_n_0_n;
sadd Uaddl_1_n_0_n (.clk(clk), .ain(tree_l_0_n_0_n), .bin(tree_l_0_n_1_n), .res(tree_l_1_n_0_n) );
defparam Uaddl_1_n_0_n.IN_WIDTH = 14;
defparam Uaddl_1_n_0_n.PIPE_DEPTH = 1;

wire [14:0] mac_res;
assign mac_res=tree_l_1_n_0_n;
wire [14:0] atree_res;
mac_tl Umtl (.clk(clk), 
             .data_in(mac_res),
             .data_out(atree_res));
defparam Umtl.DATA_WIDTH = 15;

// ---- Adder Tree Complete ---- 


wire [11:0] shft;
wire [15:0] accum;
scale_accum Usa (.clk(clk), .rst(sa_rst), .inv(sa_inv), .ain(atree_res), .accum_out(accum) );
defparam Usa.WIDTH_A = 15;


ser_shft Usershft(.clk(clk), .rst(1'b0), .ain(accum[0]), .shft_out(shft) );
defparam Usershft.SHIFT_WIDTH = 12;


wire    [27:0] fir_int_res;
scale_shft_comb Usscx (.clk(clk), .ce(done_int), .accum(accum), .shft(shft), .res(fir_int_res) );
defparam Usscx.WIDTH_ACCM = 16;
defparam Usscx.WIDTH_SHFT = 12;
defparam Usscx.WIDTH_RES = 28;

assign fir_result = fir_int_res[ACCUM_WIDTH-1:0];
assign done = done_int;
assign rdy_to_ld = rdy_int;
ser_ctrl_nc Usc (.rst(rst), .clk(clk), .clk_en(clk_en), 
              .pre_rdy(pre_rdy), 
              .sa_rst_out(sa_rst), .ser_inv_out(sa_inv), 
              .rdy_to_ld(rdy_int), 
              .tdl_ld(tdl_ld), .done(done_int) ); 

defparam Usc.REG_LEN =13; 
defparam Usc.PIPE_DLY =7; 
defparam Usc.RST_DLY =6; 
defparam Usc.INV_DLY =7; 
defparam Usc.DONE_DLY =5; 

endmodule