fir_top.tan.rpt

Altera FPGA CPLD设计高级篇电子书籍

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+----------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                               ;
+-----------------------------------------------------------------------------------------
; Option                                                ; Setting            ; From ; To ;
+-------------------------------------------------------+--------------------+------+----+
; Device name                                           ; EP1S10B672C6       ;      ;    ;
; Report IO Paths Separately                            ; Off                ;      ;    ;
; Ignore user-defined clock settings                    ; Off                ;      ;    ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;
; Cut off clear and preset signal paths                 ; On                 ;      ;    ;
; Cut off read during write signal paths                ; On                 ;      ;    ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;
; Run Minimum Analysis                                  ; On                 ;      ;    ;
; Use Minimum Timing Models                             ; Off                ;      ;    ;
; Number of paths to report                             ; 200                ;      ;    ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;
+-------------------------------------------------------+--------------------+------+----+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                       ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
; Type                   ; Slack ; Required Time ; Actual Time                      ; From                                                                                                                                                        ; To                                                                                                                                                          ;
+------------------------+-------+---------------+----------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Worst-case tsu         ; N/A   ; None          ; 2.507 ns                         ; data_in[4]                                                                                                                                                  ; fir_top_st:fir_top_st_component|par_ld_ser_tdl_nc:Utdl_0_a|data_reg[4]                                                                                      ;
; Worst-case tco         ; N/A   ; None          ; 8.052 ns                         ; fir_top_st:fir_top_st_component|ser_ctrl_nc:Usc|tdl_wait[12]                                                                                                ; rdy_to_ld                                                                                                                                                   ;
; Worst-case th          ; N/A   ; None          ; -2.021 ns                        ; data_in[9]                                                                                                                                                  ; fir_top_st:fir_top_st_component|par_ld_ser_tdl_nc:Utdl_0_a|data_reg[9]                                                                                      ;
; Worst-case minimum tco ; N/A   ; None          ; 6.881 ns                         ; fir_top_st:fir_top_st_component|scale_shft_comb:Usscx|res[24]~reg0                                                                                          ; fir_result[24]                                                                                                                                              ;
; Clock Setup: 'clock'   ; N/A   ; None          ; 255.56 MHz ( period = 3.913 ns ) ; fir_top_st:fir_top_st_component|ram_lut:Ur2_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_6m41:auto_generated|ram_block1a0~porta_datain_reg0 ; fir_top_st:fir_top_st_component|ram_lut:Ur2_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_6m41:auto_generated|ram_block1a0~porta_memory_reg0 ;
+------------------------+-------+---------------+----------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+