lockit.tan.qmsg

Altera FPGA CPLD设计高级篇电子书籍

{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "fir_clock fir_result_a\[2\] fir_top:inst1\|fir_top_st:fir_top_st_component\|scale_shft_comb:Usscx\|res\[2\]~reg0 7.022 ns register " "Info: Minimum tco from clock fir_clock to destination pin fir_result_a\[2\] through register fir_top:inst1\|fir_top_st:fir_top_st_component\|scale_shft_comb:Usscx\|res\[2\]~reg0 is 7.022 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "fir_clock source 2.871 ns + Shortest register " "Info: + Shortest clock path from clock fir_clock to source register is 2.871 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.662 ns) 0.662 ns fir_clock 1 CLK Pin_M24 1630 " "Info: 1: + IC(0.000 ns) + CELL(0.662 ns) = 0.662 ns; Loc. = Pin_M24; Fanout = 1630; CLK Node = 'fir_clock'" {  } { { "D:/prj_D/LogicLock/LogicLock/db/lockit_cmp.qrpt" "" "" { Report "D:/prj_D/LogicLock/LogicLock/db/lockit_cmp.qrpt" Compiler "lockit" "UNKNOWN" "V1" "D:/prj_D/LogicLock/LogicLock/db/lockit.quartus_db" { Floorplan "" "" "" { fir_clock } "NODE_NAME" } } } { "D:/prj_D/LogicLock/LogicLock/lockit.bdf" "" "" { Schematic "D:/prj_D/LogicLock/LogicLock/lockit.bdf" { { -184 -56 112 -168 "fir_clock" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.649 ns) + CELL(0.560 ns) 2.871 ns fir_top:inst1\|fir_top_st:fir_top_st_component\|scale_shft_comb:Usscx\|res\[2\]~reg0 2 REG LC_X41_Y25_N4 1 " "Info: 2: + IC(1.649 ns) + CELL(0.560 ns) = 2.871 ns; Loc. = LC_X41_Y25_N4; Fanout = 1; REG Node = 'fir_top:inst1\|fir_top_st:fir_top_st_component\|scale_shft_comb:Usscx\|res\[2\]~reg0'" {  } { { "D:/prj_D/LogicLock/LogicLock/db/lockit_cmp.qrpt" "" "" { Report "D:/prj_D/LogicLock/LogicLock/db/lockit_cmp.qrpt" Compiler "lockit" "UNKNOWN" "V1" "D:/prj_D/LogicLock/LogicLock/db/lockit.quartus_db" { Floorplan "" "" "2.209 ns" { fir_clock fir_top:inst1|fir_top_st:fir_top_st_component|scale_shft_comb:Usscx|res[2]~reg0 } "NODE_NAME" } } } { "D:/prj_D/LogicLock/LogicLock/fir/atom_netlists/fir_top.vqm" "" "" { Text "D:/prj_D/LogicLock/LogicLock/fir/atom_netlists/fir_top.vqm" 901 74 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.222 ns 42.56 % " "Info: Total cell delay = 1.222 ns ( 42.56 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.649 ns 57.44 % " "Info: Total interconnect delay = 1.649 ns ( 57.44 % )" {  } {  } 0}  } { { "D:/prj_D/LogicLock/LogicLock/db/lockit_cmp.qrpt" "" "" { Report "D:/prj_D/LogicLock/LogicLock/db/lockit_cmp.qrpt" Compiler "lockit" "UNKNOWN" "V1" "D:/prj_D/LogicLock/LogicLock/db/lockit.quartus_db" { Floorplan "" "" "2.871 ns" { fir_clock fir_top:inst1|fir_top_st:fir_top_st_component|scale_shft_comb:Usscx|res[2]~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.176 ns + " "Info: + Micro clock to output delay of source is 0.176 ns" {  } { { "D:/prj_D/LogicLock/LogicLock/fir/atom_netlists/fir_top.vqm" "" "" { Text "D:/prj_D/LogicLock/LogicLock/fir/atom_netlists/fir_top.vqm" 901 74 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.975 ns + Shortest register pin " "Info: + Shortest register to pin delay is 3.975 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns fir_top:inst1\|fir_top_st:fir_top_st_component\|scale_shft_comb:Usscx\|res\[2\]~reg0 1 REG LC_X41_Y25_N4 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X41_Y25_N4; Fanout = 1; REG Node = 'fir_top:inst1\|fir_top_st:fir_top_st_component\|scale_shft_comb:Usscx\|res\[2\]~reg0'" {  } { { "D:/prj_D/LogicLock/LogicLock/db/lockit_cmp.qrpt" "" "" { Report "D:/prj_D/LogicLock/LogicLock/db/lockit_cmp.qrpt" Compiler "lockit" "UNKNOWN" "V1" "D:/prj_D/LogicLock/LogicLock/db/lockit.quartus_db" { Floorplan "" "" "" { fir_top:inst1|fir_top_st:fir_top_st_component|scale_shft_comb:Usscx|res[2]~reg0 } "NODE_NAME" } } } { "D:/prj_D/LogicLock/LogicLock/fir/atom_netlists/fir_top.vqm" "" "" { Text "D:/prj_D/LogicLock/LogicLock/fir/atom_netlists/fir_top.vqm" 901 74 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.475 ns) + CELL(2.500 ns) 3.975 ns fir_result_a\[2\] 2 PIN Pin_K19 0 " "Info: 2: + IC(1.475 ns) + CELL(2.500 ns) = 3.975 ns; Loc. = Pin_K19; Fanout = 0; PIN Node = 'fir_result_a\[2\]'" {  } { { "D:/prj_D/LogicLock/LogicLock/db/lockit_cmp.qrpt" "" "" { Report "D:/prj_D/LogicLock/LogicLock/db/lockit_cmp.qrpt" Compiler "lockit" "UNKNOWN" "V1" "D:/prj_D/LogicLock/LogicLock/db/lockit.quartus_db" { Floorplan "" "" "3.975 ns" { fir_top:inst1|fir_top_st:fir_top_st_component|scale_shft_comb:Usscx|res[2]~reg0 fir_result_a[2] } "NODE_NAME" } } } { "D:/prj_D/LogicLock/LogicLock/lockit.bdf" "" "" { Schematic "D:/prj_D/LogicLock/LogicLock/lockit.bdf" { { -232 416 598 -216 "fir_result_a\[26..0\]" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.500 ns 62.89 % " "Info: Total cell delay = 2.500 ns ( 62.89 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.475 ns 37.11 % " "Info: Total interconnect delay = 1.475 ns ( 37.11 % )" {  } {  } 0}  } { { "D:/prj_D/LogicLock/LogicLock/db/lockit_cmp.qrpt" "" "" { Report "D:/prj_D/LogicLock/LogicLock/db/lockit_cmp.qrpt" Compiler "lockit" "UNKNOWN" "V1" "D:/prj_D/LogicLock/LogicLock/db/lockit.quartus_db" { Floorplan "" "" "3.975 ns" { fir_top:inst1|fir_top_st:fir_top_st_component|scale_shft_comb:Usscx|res[2]~reg0 fir_result_a[2] } "NODE_NAME" } } }  } 0}  } { { "D:/prj_D/LogicLock/LogicLock/db/lockit_cmp.qrpt" "" "" { Report "D:/prj_D/LogicLock/LogicLock/db/lockit_cmp.qrpt" Compiler "lockit" "UNKNOWN" "V1" "D:/prj_D/LogicLock/LogicLock/db/lockit.quartus_db" { Floorplan "" "" "2.871 ns" { fir_clock fir_top:inst1|fir_top_st:fir_top_st_component|scale_shft_comb:Usscx|res[2]~reg0 } "NODE_NAME" } } } { "D:/prj_D/LogicLock/LogicLock/db/lockit_cmp.qrpt" "" "" { Report "D:/prj_D/LogicLock/LogicLock/db/lockit_cmp.qrpt" Compiler "lockit" "UNKNOWN" "V1" "D:/prj_D/LogicLock/LogicLock/db/lockit.quartus_db" { Floorplan "" "" "3.975 ns" { fir_top:inst1|fir_top_st:fir_top_st_component|scale_shft_comb:Usscx|res[2]~reg0 fir_result_a[2] } "NODE_NAME" } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Dec 15 04:59:40 2004 " "Info: Processing ended: Wed Dec 15 04:59:40 2004" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}