lockit.tan.rpt

Altera FPGA CPLD设计高级篇电子书籍

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+----------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                               ;
+-----------------------------------------------------------------------------------------
; Option                                                ; Setting            ; From ; To ;
+-------------------------------------------------------+--------------------+------+----+
; Device name                                           ; EP1S10B672C6       ;      ;    ;
; Report IO Paths Separately                            ; Off                ;      ;    ;
; Ignore user-defined clock settings                    ; Off                ;      ;    ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;
; Cut off clear and preset signal paths                 ; On                 ;      ;    ;
; Cut off read during write signal paths                ; On                 ;      ;    ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;
; Run Minimum Analysis                                  ; On                 ;      ;    ;
; Use Minimum Timing Models                             ; Off                ;      ;    ;
; Number of paths to report                             ; 200                ;      ;    ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;
+-------------------------------------------------------+--------------------+------+----+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                                              ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
; Type                     ; Slack ; Required Time ; Actual Time                      ; From                                                                                                                                                                    ; To                                                                                                                                                                   ;
+--------------------------+-------+---------------+----------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Worst-case tsu           ; N/A   ; None          ; 5.587 ns                         ; fifo_wr                                                                                                                                                                 ; data_buffer:inst|scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|ram_block2a11~Iporta_we_reg     ;
; Worst-case tco           ; N/A   ; None          ; 13.684 ns                        ; data_buffer:inst|scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|ram_block2a14~Iportb_address_reg11 ; fifo_out[6]                                                                                                                                                          ;
; Worst-case th            ; N/A   ; None          ; -2.241 ns                        ; fir_data_b[8]                                                                                                                                                           ; fir_top:inst2|fir_top_st:fir_top_st_component|par_ld_ser_tdl_nc:Utdl_0_a|data_reg[8]                                                                                 ;
; Worst-case minimum tco   ; N/A   ; None          ; 7.022 ns                         ; fir_top:inst1|fir_top_st:fir_top_st_component|scale_shft_comb:Usscx|res[2]~reg0                                                                                         ; fir_result_a[2]                                                                                                                                                      ;
; Clock Setup: 'fifo_clk'  ; N/A   ; None          ; 245.34 MHz ( period = 4.076 ns ) ; data_buffer:inst|scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|b_full                                                   ; data_buffer:inst|scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|ram_block2a11~Iporta_we_reg     ;