lockit.map.rpt

Altera FPGA CPLD设计高级篇电子书籍

+--------------------------------------------------+
; Analysis & Synthesis Files Read                  ;
+---------------------------------------------------
; File Name                                 ; Read ;
+-------------------------------------------+------+
; fir/atom_netlists/fir_top.vqm             ; Read ;
; data_buffer/atom_netlists/data_buffer.vqm ; Read ;
; D:/prj_D/LogicLock/LogicLock/lockit.bdf   ; Read ;
+-------------------------------------------+------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+----------------------------------------------
; Resource                      ; Usage       ;
+-------------------------------+-------------+
; Logic cells                   ; 1,388       ;
; Total combinational functions ; 914         ;
; Total registers               ; 1362        ;
; I/O pins                      ; 105         ;
; Total memory bits             ; 79040       ;
; Maximum fan-out node          ; fir_clock   ;
; Maximum fan-out               ; 1396        ;
; Total fan-out                 ; 4682        ;
; Average fan-out               ; 2.95        ;
+-------------------------------+-------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary                                                                                                                                                                                                                                         ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
; Name                                                                                                                                                  ; Type ; Mode             ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size  ; MIF                ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+--------------------+
; data_buffer:inst|scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|ALTSYNCRAM       ; M4K  ; Simple Dual Port ; 8192         ; 8            ; 8192         ; 8            ; 65536 ; None               ;
; fir_top:inst1|fir_top_st:fir_top_st_component|ram_lut:Ur0_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_qs41:auto_generated|ALTSYNCRAM ; M4K  ; Simple Dual Port ; 256          ; 13           ; 256          ; 13           ; 3328  ; fir_top_coef_0.mif ;
; fir_top:inst1|fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|ALTSYNCRAM ; M4K  ; Simple Dual Port ; 256          ; 13           ; 256          ; 13           ; 3328  ; fir_top_coef_1.mif ;
; fir_top:inst1|fir_top_st:fir_top_st_component|ram_lut:Ur2_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_6m41:auto_generated|ALTSYNCRAM ; M4K  ; Simple Dual Port ; 8            ; 12           ; 8            ; 12           ; 96    ; fir_top_coef_2.mif ;
; fir_top:inst2|fir_top_st:fir_top_st_component|ram_lut:Ur0_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_qs41:auto_generated|ALTSYNCRAM ; M4K  ; Simple Dual Port ; 256          ; 13           ; 256          ; 13           ; 3328  ; fir_top_coef_0.mif ;
; fir_top:inst2|fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|ALTSYNCRAM ; M4K  ; Simple Dual Port ; 256          ; 13           ; 256          ; 13           ; 3328  ; fir_top_coef_1.mif ;
; fir_top:inst2|fir_top_st:fir_top_st_component|ram_lut:Ur2_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_6m41:auto_generated|ALTSYNCRAM ; M4K  ; Simple Dual Port ; 8            ; 12           ; 8            ; 12           ; 96    ; fir_top_coef_2.mif ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+--------------------+


+----------------------------------------------------------------+
; WYSIWYG Cells                                                  ;
+-----------------------------------------------------------------
; Statistic                                              ; Value ;
+--------------------------------------------------------+-------+
; Number of WYSIWYG cells                                ; 1388  ;
; Number of synthesis-generated cells                    ; 0     ;
; Number of WYSIWYG LUTs                                 ; 914   ;
; Number of synthesis-generated LUTs                     ; 0     ;
; Number of WYSIWYG registers                            ; 1362  ;
; Number of synthesis-generated registers                ; 0     ;
; Number of cells with combinational logic only          ; 26    ;
; Number of cells with registers only                    ; 474   ;
; Number of cells with combinational logic and registers ; 888   ;
+--------------------------------------------------------+-------+


+----------------------------------------------+
; General Register Statistics                  ;
+-----------------------------------------------
; Statistic                            ; Value ;
+--------------------------------------+-------+
; Number of registers using SCLR       ; 0     ;
; Number of registers using SLOAD      ; 32    ;
; Number of registers using ACLR       ; 28    ;
; Number of registers using ALOAD      ; 0     ;
; Number of registers using CLK_ENABLE ; 68    ;
; Number of registers using OE         ; 0     ;
; Number of registers using PRESET     ; 0     ;
+--------------------------------------+-------+


+--------------------------------+
; Analysis & Synthesis Messages  ;
+--------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.0 Build 190 1/28/2004 SJ Full Version
    Info: Processing started: Wed Dec 15 04:58:03 2004
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off lockit -c lockit
Warning: Can't find license for core FIR Compiler v2.7.0beta (6AF7_0012)
Warning: Can't find license for core FIR Compiler v2.7.0beta (6AF7_0012)
Warning: Can't find license for core FIR Compiler v2.7.0beta (6AF7_0012)
Warning: Can't find license for core