lockit.map.rpt

Altera FPGA CPLD设计高级篇电子书籍

; Limit AHDL Integers to 32 Bits                          ; Off          ; Off           ;
; Ignore SOFT Buffers                                     ; On           ; On            ;
; Ignore LCELL Buffers                                    ; Off          ; Off           ;
; Ignore ROW GLOBAL Buffers                               ; Off          ; Off           ;
; Ignore GLOBAL Buffers                                   ; Off          ; Off           ;
; Ignore CASCADE Buffers                                  ; Off          ; Off           ;
; Ignore CARRY Buffers                                    ; Off          ; Off           ;
; Remove Duplicate Registers                              ; On           ; On            ;
; Remove Redundant Logic Cells                            ; Off          ; Off           ;
; Power-Up Don't Care                                     ; On           ; On            ;
; NOT Gate Push-Back                                      ; On           ; On            ;
; DSP Block Balancing                                     ; Auto         ; Auto          ;
; State Machine Processing                                ; Auto         ; Auto          ;
; Family name                                             ; Stratix      ; Stratix       ;
; VHDL Version                                            ; VHDL93       ; VHDL93        ;
; Verilog Version                                         ; Verilog_2001 ; Verilog_2001  ;
; Preserve fewer node names                               ; On           ; On            ;
; Disk space/compilation speed tradeoff                   ; Normal       ; Normal        ;
; Create Debugging Nodes for IP Cores                     ; off          ; off           ;
+---------------------------------------------------------+--------------+---------------+


+-------------------------------------------------+
; Analysis & Synthesis Default Parameter Settings ;
+--------------------------------------------------
; Name               ; Setting                    ;
+--------------------+----------------------------+
; CARRY_CHAIN        ; MANUAL                     ;
; CASCADE_CHAIN      ; MANUAL                     ;
; OPTIMIZE_FOR_SPEED ; 5                          ;
; STYLE              ; FAST                       ;
+--------------------+----------------------------+


+------------+
; Hierarchy  ;
+------------+
lockit
 |-- data_buffer:inst
      |-- scfifo:scfifo_component
           |-- scfifo_39m:auto_generated
                |-- a_dpfifo_ihi:dpfifo
                     |-- dpram_btj:FIFOram
                          |-- altsyncram_9kb1:altsyncram1
                               |-- decode_4r6:decode3
                               |-- mux_kl7:mux4
                     |-- a_fefifo_n4f:fifo_state
                          |-- lpm_counter:count_usedw
                               |-- alt_counter_stratix:wysi_counter
                     |-- lpm_counter:rd_ptr_count
                          |-- alt_counter_stratix:wysi_counter
                     |-- lpm_counter:wr_ptr
                          |-- alt_counter_stratix:wysi_counter
 |-- fir_top:inst1
      |-- fir_top_st:fir_top_st_component
           |-- sadd:Uaddl_0_n_0_n
           |-- sadd:Uaddl_0_n_1_n
           |-- sadd:Uaddl_1_n_0_n
           |-- ram_lut:Ur0_n
                |-- ram_2pt_var:ram
                     |-- altsyncram:altsyncram_component
                          |-- altsyncram_qs41:auto_generated
           |-- ram_lut:Ur1_n
                |-- ram_2pt_var:ram
                     |-- altsyncram:altsyncram_component
                          |-- altsyncram_rs41:auto_generated
           |-- ram_lut:Ur2_n
                |-- ram_2pt_var:ram
                     |-- altsyncram:altsyncram_component
                          |-- altsyncram_6m41:auto_generated
           |-- scale_accum:Usa
           |-- ser_ctrl_nc:Usc
           |-- ser_shft:Usershft
           |-- scale_shft_comb:Usscx
           |-- par_ld_ser_tdl_nc:Utdl_0_a
           |-- lc_tdl_strat:Utdl_0_n
           |-- lc_tdl_strat:Utdl_1_n
           |-- lc_tdl_strat:Utdl_2_n
           |-- sym_add_ser:sym_0_n
           |-- sym_add_ser:sym_1_n
           |-- sym_add_ser:sym_2_n
           |-- sym_add_ser:sym_3_n
           |-- sym_add_ser:sym_4_n
           |-- sym_add_ser:sym_5_n
           |-- sym_add_ser:sym_6_n
           |-- sym_add_ser:sym_7_n
           |-- sym_add_ser:sym_8_n