lockit.fit.eqn

Altera FPGA CPLD设计高级篇电子书籍

--C2L24 is fir_top:inst2|~GND at LC_X17_Y27_N1
--operation mode is normal

C2L24 = AMPP_FUNCTION();


--U2L3 is fir_top:inst2|fir_top_st:fir_top_st_component|ser_ctrl_nc:Usc|i~85 at LC_X18_Y30_N3
--operation mode is normal

U2L3 = AMPP_FUNCTION(U2_tdl_wait[4], U2_tdl_wait[1], U2_tdl_wait[3]);

--U2_tdl_wait[2] is fir_top:inst2|fir_top_st:fir_top_st_component|ser_ctrl_nc:Usc|tdl_wait[2] at LC_X18_Y30_N3
--operation mode is normal

U2_tdl_wait[2] = AMPP_FUNCTION(fir_clock, U2_tdl_wait[3], !sys_rst, GND);


--U2L1 is fir_top:inst2|fir_top_st:fir_top_st_component|ser_ctrl_nc:Usc|i~83 at LC_X18_Y27_N3
--operation mode is normal

U2L1 = AMPP_FUNCTION(U2_tdl_wait[5], U2_tdl_wait[12], U2_tdl_wait[6]);

--U2_tdl_wait[11] is fir_top:inst2|fir_top_st:fir_top_st_component|ser_ctrl_nc:Usc|tdl_wait[11] at LC_X18_Y27_N3
--operation mode is normal

U2_tdl_wait[11] = AMPP_FUNCTION(fir_clock, U2_tdl_wait[12], !sys_rst, GND);


--U2L2 is fir_top:inst2|fir_top_st:fir_top_st_component|ser_ctrl_nc:Usc|i~84 at LC_X18_Y27_N1
--operation mode is normal

U2L2 = AMPP_FUNCTION(U2_tdl_wait[9], U2_tdl_wait[10], U2_tdl_wait[8]);

--U2_tdl_wait[7] is fir_top:inst2|fir_top_st:fir_top_st_component|ser_ctrl_nc:Usc|tdl_wait[7] at LC_X18_Y27_N1
--operation mode is normal

U2_tdl_wait[7] = AMPP_FUNCTION(fir_clock, U2_tdl_wait[8], !sys_rst, GND);


--U2_tdl_rdy is fir_top:inst2|fir_top_st:fir_top_st_component|ser_ctrl_nc:Usc|tdl_rdy at LC_X18_Y27_N5
--operation mode is normal

U2_tdl_rdy = AMPP_FUNCTION(fir_clock, U2L1, U2_tdl_wait[0], U2L2, U2L3, !sys_rst);


--U2_tdl_wait[12] is fir_top:inst2|fir_top_st:fir_top_st_component|ser_ctrl_nc:Usc|tdl_wait[12] at LC_X18_Y28_N5
--operation mode is normal

U2_tdl_wait[12] = AMPP_FUNCTION(fir_clock, U2_tdl_rdy, !sys_rst);


--U2_tdl_wait[10] is fir_top:inst2|fir_top_st:fir_top_st_component|ser_ctrl_nc:Usc|tdl_wait[10] at LC_X18_Y27_N6
--operation mode is normal

U2_tdl_wait[10] = AMPP_FUNCTION(fir_clock, U2_tdl_wait[11], !sys_rst, GND);


--U2_tdl_wait[9] is fir_top:inst2|fir_top_st:fir_top_st_component|ser_ctrl_nc:Usc|tdl_wait[9] at LC_X18_Y27_N8
--operation mode is normal

U2_tdl_wait[9] = AMPP_FUNCTION(fir_clock, U2_tdl_wait[10], !sys_rst);


--U2_tdl_wait[8] is fir_top:inst2|fir_top_st:fir_top_st_component|ser_ctrl_nc:Usc|tdl_wait[8] at LC_X18_Y27_N9
--operation mode is normal

U2_tdl_wait[8] = AMPP_FUNCTION(fir_clock, U2_tdl_wait[9], !sys_rst);


--U2_tdl_wait[6] is fir_top:inst2|fir_top_st:fir_top_st_component|ser_ctrl_nc:Usc|tdl_wait[6] at LC_X18_Y27_N0
--operation mode is normal

U2_tdl_wait[6] = AMPP_FUNCTION(fir_clock, U2_tdl_wait[7], !sys_rst, GND);


--U2_tdl_wait[5] is fir_top:inst2|fir_top_st:fir_top_st_component|ser_ctrl_nc:Usc|tdl_wait[5] at LC_X18_Y27_N2
--operation mode is normal

U2_tdl_wait[5] = AMPP_FUNCTION(fir_clock, U2_tdl_wait[6], !sys_rst);


--U2_tdl_wait[4] is fir_top:inst2|fir_top_st:fir_top_st_component|ser_ctrl_nc:Usc|tdl_wait[4] at LC_X18_Y30_N7
--operation mode is normal

U2_tdl_wait[4] = AMPP_FUNCTION(fir_clock, U2_tdl_wait[5], !sys_rst, GND);


--U2_tdl_wait[3] is fir_top:inst2|fir_top_st:fir_top_st_component|ser_ctrl_nc:Usc|tdl_wait[3] at LC_X19_Y30_N9
--operation mode is normal

U2_tdl_wait[3] = AMPP_FUNCTION(fir_clock, U2_tdl_wait[4], !sys_rst);


--U2_tdl_wait[1] is fir_top:inst2|fir_top_st:fir_top_st_component|ser_ctrl_nc:Usc|tdl_wait[1] at LC_X18_Y30_N0
--operation mode is normal

U2_tdl_wait[1] = AMPP_FUNCTION(fir_clock, U2_tdl_wait[2], !sys_rst, GND);


--U2_tdl_wait[0] is fir_top:inst2|fir_top_st:fir_top_st_component|ser_ctrl_nc:Usc|tdl_wait[0] at LC_X18_Y30_N5
--operation mode is normal

U2_tdl_wait[0] = AMPP_FUNCTION(fir_clock, U2_tdl_wait[1], !sys_rst, GND);


--X2_data_reg[12] is fir_top:inst2|fir_top_st:fir_top_st_component|par_ld_ser_tdl_nc:Utdl_0_a|data_reg[12] at LC_X17_Y27_N0
--operation mode is normal

X2_data_reg[12] = AMPP_FUNCTION(fir_clock, U2_tdl_wait[0], fir_data_b[11], VCC);


--X2_data_reg[11] is fir_top:inst2|fir_top_st:fir_top_st_component|par_ld_ser_tdl_nc:Utdl_0_a|data_reg[11] at LC_X17_Y29_N2
--operation mode is normal

X2_data_reg[11] = AMPP_FUNCTION(fir_clock, U2_tdl_wait[0], X2_data_reg[12], fir_data_b[11], VCC);


--X2_data_reg[10] is fir_top:inst2|fir_top_st:fir_top_st_component|par_ld_ser_tdl_nc:Utdl_0_a|data_reg[10] at LC_X18_Y30_N6
--operation mode is normal

X2_data_reg[10] = AMPP_FUNCTION(fir_clock, X2_data_reg[11], U2_tdl_wait[0], fir_data_b[10], VCC);


--X2_data_reg[9] is fir_top:inst2|fir_top_st:fir_top_st_component|par_ld_ser_tdl_nc:Utdl_0_a|data_reg[9] at LC_X18_Y30_N9
--operation mode is normal

X2_data_reg[9] = AMPP_FUNCTION(fir_clock, X2_data_reg[10], U2_tdl_wait[0], fir_data_b[9], VCC);


--X2_data_reg[8] is fir_top:inst2|fir_top_st:fir_top_st_component|par_ld_ser_tdl_nc:Utdl_0_a|data_reg[8] at LC_X18_Y30_N8
--operation mode is normal

X2_data_reg[8] = AMPP_FUNCTION(fir_clock, X2_data_reg[9], U2_tdl_wait[0], fir_data_b[8], VCC);


--X2_data_reg[7] is fir_top:inst2|fir_top_st:fir_top_st_component|par_ld_ser_tdl_nc:Utdl_0_a|data_reg[7] at LC_X18_Y30_N4
--operation mode is normal

X2_data_reg[7] = AMPP_FUNCTION(fir_clock, X2_data_reg[8], U2_tdl_wait[0], fir_data_b[7], VCC);


--X2_data_reg[6] is fir_top:inst2|fir_top_st:fir_top_st_component|par_ld_ser_tdl_nc:Utdl_0_a|data_reg[6] at LC_X18_Y30_N1
--operation mode is normal

X2_data_reg[6] = AMPP_FUNCTION(fir_clock, X2_data_reg[7], U2_tdl_wait[0], fir_data_b[6], VCC);


--X2_data_reg[5] is fir_top:inst2|fir_top_st:fir_top_st_component|par_ld_ser_tdl_nc:Utdl_0_a|data_reg[5] at LC_X18_Y30_N2
--operation mode is normal

X2_data_reg[5] = AMPP_FUNCTION(fir_clock, X2_data_reg[6], U2_tdl_wait[0], fir_data_b[5], VCC);


--X2_data_reg[4] is fir_top:inst2|fir_top_st:fir_top_st_component|par_ld_ser_tdl_nc:Utdl_0_a|data_reg[4] at LC_X17_Y30_N2
--operation mode is normal

X2_data_reg[4] = AMPP_FUNCTION(fir_clock, U2_tdl_wait[0], X2_data_reg[5], fir_data_b[4], VCC);


--X2_data_reg[3] is fir_top:inst2|fir_top_st:fir_top_st_component|par_ld_ser_tdl_nc:Utdl_0_a|data_reg[3] at LC_X17_Y29_N9
--operation mode is normal

X2_data_reg[3] = AMPP_FUNCTION(fir_clock, X2_data_reg[4], U2_tdl_wait[0], fir_data_b[3], VCC);


--X2_data_reg[2] is fir_top:inst2|fir_top_st:fir_top_st_component|par_ld_ser_tdl_nc:Utdl_0_a|data_reg[2] at LC_X17_Y29_N6
--operation mode is normal

X2_data_reg[2] = AMPP_FUNCTION(fir_clock, X2_data_reg[3], U2_tdl_wait[0], fir_data_b[2], VCC);


--X2_data_reg[1] is fir_top:inst2|fir_top_st:fir_top_st_component|par_ld_ser_tdl_nc:Utdl_0_a|data_reg[1] at LC_X17_Y29_N5
--operation mode is normal

X2_data_reg[1] = AMPP_FUNCTION(fir_clock, X2_data_reg[2], U2_tdl_wait[0], fir_data_b[1], VCC);


--X2_data_reg[0] is fir_top:inst2|fir_top_st:fir_top_st_component|par_ld_ser_tdl_nc:Utdl_0_a|data_reg[0] at LC_X17_Y29_N1
--operation mode is normal

X2_data_reg[0] = AMPP_FUNCTION(fir_clock, X2_data_reg[1], U2_tdl_wait[0], fir_data_b[0], VCC);


--X2_add_dly2[1] is fir_top:inst2|fir_top_st:fir_top_st_component|par_ld_ser_tdl_nc:Utdl_0_a|add_dly2[1] at LC_X17_Y28_N7
--operation mode is normal

X2_add_dly2[1] = AMPP_FUNCTION(fir_clock, X2_data_reg[0], VCC, GND);


--Y4_sft00_n[12] is fir_top:inst2|fir_top_st:fir_top_st_component|lc_tdl_strat:Utdl_0_n|sft00_n[12] at LC_X19_Y24_N3
--operation mode is normal

Y4_sft00_n[12] = AMPP_FUNCTION(fir_clock, X2_add_dly2[1], VCC, GND);


--Y4_sft00_n[11] is fir_top:inst2|fir_top_st:fir_top_st_component|lc_tdl_strat:Utdl_0_n|sft00_n[11] at LC_X19_Y24_N7
--operation mode is normal

Y4_sft00_n[11] = AMPP_FUNCTION(fir_clock, Y4_sft00_n[12], VCC, GND);


--Y4_sft00_n[10] is fir_top:inst2|fir_top_st:fir_top_st_component|lc_tdl_strat:Utdl_0_n|sft00_n[10] at LC_X19_Y24_N6
--operation mode is normal

Y4_sft00_n[10] = AMPP_FUNCTION(fir_clock, Y4_sft00_n[11], VCC, GND);


--Y4_sft00_n[9] is fir_top:inst2|fir_top_st:fir_top_st_component|lc_tdl_strat:Utdl_0_n|sft00_n[9] at LC_X18_Y24_N9
--operation mode is normal

Y4_sft00_n[9] = AMPP_FUNCTION(fir_clock, Y4_sft00_n[10], VCC, GND);


--Y4_sft00_n[8] is fir_top:inst2|fir_top_st:fir_top_st_component|lc_tdl_strat:Utdl_0_n|sft00_n[8] at LC_X18_Y24_N3
--operation mode is normal

Y4_sft00_n[8] = AMPP_FUNCTION(fir_clock, Y4_sft00_n[9], VCC);


--Y4_sft00_n[7] is fir_top:inst2|fir_top_st:fir_top_st_component|lc_tdl_strat:Utdl_0_n|sft00_n[7] at LC_X18_Y24_N0
--operation mode is normal

Y4_sft00_n[7] = AMPP_FUNCTION(fir_clock, Y4_sft00_n[8], VCC, GND);


--Y4_sft00_n[6] is fir_top:inst2|fir_top_st:fir_top_st_component|lc_tdl_strat:Utdl_0_n|sft00_n[6] at LC_X18_Y24_N7
--operation mode is normal

Y4_sft00_n[6] = AMPP_FUNCTION(fir_clock, Y4_sft00_n[7], VCC);


--Y4_sft00_n[5] is fir_top:inst2|fir_top_st:fir_top_st_component|lc_tdl_strat:Utdl_0_n|sft00_n[5] at LC_X18_Y24_N5
--operation mode is normal

Y4_sft00_n[5] = AMPP_FUNCTION(fir_clock, Y4_sft00_n[6], VCC, GND);


--Y4_sft00_n[4] is fir_top:inst2|fir_top_st:fir_top_st_component|lc_tdl_strat:Utdl_0_n|sft00_n[4] at LC_X18_Y24_N1
--operation mode is normal

Y4_sft00_n[4] = AMPP_FUNCTION(fir_clock, Y4_sft00_n[5], VCC, GND);


--Y4_sft00_n[3] is fir_top:inst2|fir_top_st:fir_top_st_component|lc_tdl_strat:Utdl_0_n|sft00_n[3] at LC_X18_Y24_N4
--operation mode is normal

Y4_sft00_n[3] = AMPP_FUNCTION(fir_clock, Y4_sft00_n[4], VCC, GND);


--Y4_sft00_n[2] is fir_top:inst2|fir_top_st:fir_top_st_component|lc_tdl_strat:Utdl_0_n|sft00_n[2] at LC_X14_Y24_N0
--operation mode is normal

Y4_sft00_n[2] = AMPP_FUNCTION(fir_clock, Y4_sft00_n[3], VCC, GND);


--Y4_sft00_n[1] is fir_top:inst2|fir_top_st:fir_top_st_component|lc_tdl_strat:Utdl_0_n|sft00_n[1] at LC_X14_Y24_N3
--operation mode is normal

Y4_sft00_n[1] = AMPP_FUNCTION(fir_clock, Y4_sft00_n[2], VCC);


--Y4_sft00_n[0] is fir_top:inst2|fir_top_st:fir_top_st_component|lc_tdl_strat:Utdl_0_n|sft00_n[0] at LC_X14_Y24_N9
--operation mode is normal

Y4_sft00_n[0] = AMPP_FUNCTION(fir_clock, Y4_sft00_n[1], VCC, GND);


--Y4_sft01_n[12] is fir_top:inst2|fir_top_st:fir_top_st_component|lc_tdl_strat:Utdl_0_n|sft01_n[12] at LC_X14_Y24_N2
--operation mode is normal

Y4_sft01_n[12] = AMPP_FUNCTION(fir_clock, Y4_sft00_n[0], VCC);


--Y4_sft01_n[11] is fir_top:inst2|fir_top_st:fir_top_st_component|lc_tdl_strat:Utdl_0_n|sft01_n[11] at LC_X14_Y24_N7
--operation mode is normal

Y4_sft01_n[11] = AMPP_FUNCTION(fir_clock, Y4_sft01_n[12], VCC, GND);


--Y4_sft01_n[10] is fir_top:inst2|fir_top_st:fir_top_st_component|lc_tdl_strat:Utdl_0_n|sft01_n[10] at LC_X14_Y24_N1
--operation mode is normal

Y4_sft01_n[10] = AMPP_FUNCTION(fir_clock, Y4_sft01_n[11], VCC, GND);


--Y4_sft01_n[9] is fir_top:inst2|fir_top_st:fir_top_st_component|lc_tdl_strat:Utdl_0_n|sft01_n[9] at LC_X14_Y24_N5
--operation mode is normal

Y4_sft01_n[9] = AMPP_FUNCTION(fir_clock, Y4_sft01_n[10], VCC, GND);


--Y4_sft01_n[8] is fir_top:inst2|fir_top_st:fir_top_st_component|lc_tdl_strat:Utdl_0_n|sft01_n[8] at LC_X14_Y24_N4
--operation mode is normal

Y4_sft01_n[8] = AMPP_FUNCTION(fir_clock, Y4_sft01_n[9], VCC, GND);


--Y4_sft01_n[7] is fir_top:inst2|fir_top_st:fir_top_st_component|lc_tdl_strat:Utdl_0_n|sft01_n[7] at LC_X14_Y24_N8
--operation mode is normal

Y4_sft01_n[7] = AMPP_FUNCTION(fir_clock, Y4_sft01_n[8], VCC, GND);


--Y4_sft01_n[6] is fir_top:inst2|fir_top_st:fir_top_st_component|lc_tdl_strat:Utdl_0_n|sft01_n[6] at LC_X14_Y25_N2
--operation mode is normal

Y4_sft01_n[6] = AMPP_FUNCTION(fir_clock, Y4_sft01_n[7], VCC, GND);


--Y4_sft01_n[5] is fir_top:inst2|fir_top_st:fir_top_st_component|lc_tdl_strat:Utdl_0_n|sft01_n[5] at LC_X14_Y25_N8
--operation mode is normal

Y4_sft01_n[5] = AMPP_FUNCTION(fir_clock, Y4_sft01_n[6], VCC);


--Y4_sft01_n[4] is fir_top:inst2|fir_top_st:fir_top_st_component|lc_tdl_strat:Utdl_0_n|sft01_n[4] at LC_X14_Y25_N6
--operation mode is normal

Y4_sft01_n[4] = AMPP_FUNCTION(fir_clock, Y4_sft01_n[5], VCC);


--Y4_sft01_n[3] is fir_top:inst2|fir_top_st:fir_top_st_component|lc_tdl_strat:Utdl_0_n|sft01_n[3] at LC_X14_Y25_N0
--operation mode is normal

Y4_sft01_n[3] = AMPP_FUNCTION(fir_clock, Y4_sft01_n[4], VCC);


--Y4_sft01_n[2] is fir_top:inst2|fir_top_st:fir_top_st_component|lc_tdl_strat:Utdl_0_n|sft01_n[2] at LC_X14_Y25_N3
--operation mode is normal

Y4_sft01_n[2] = AMPP_FUNCTION(fir_clock, Y4_sft01_n[3], VCC);


--Y4_sft01_n[1] is fir_top:inst2|fir_top_st:fir_top_st_component|lc_tdl_strat:Utdl_0_n|sft01_n[1] at LC_X14_Y25_N5
--operation mode is normal

Y4_sft01_n[1] = AMPP_FUNCTION(fir_clock, Y4_sft01_n[2], VCC, GND);


--Y4_sft01_n[0] is fir_top:inst2|fir_top_st:fir_top_st_component|lc_tdl_strat:Utdl_0_n|sft01_n[0] at LC_X14_Y25_N4
--operation mode is normal

Y4_sft01_n[0] = AMPP_FUNCTION(fir_clock, Y4_sft01_n[1], VCC, GND);


--Y4_sft02_n[12] is fir_top:inst2|fir_top_st:fir_top_st_component|lc_tdl_strat:Utdl_0_n|sft02_n[12] at LC_X14_Y25_N1
--operation mode is normal

Y4_sft02_n[12] = AMPP_FUNCTION(fir_clock, Y4_sft01_n[0], VCC, GND);


--Y4_sft02_n[11] is fir_top:inst2|fir_top_st:fir_top_st_component|lc_tdl_strat:Utdl_0_n|sft02_n[11] at LC_X14_Y25_N9
--operation mode is normal

Y4_sft02_n[11] = AMPP_FUNCTION(fir_clock, Y4_sft02_n[12], VCC, GND);


--Y4_sft02_n[10] is fir_top:inst2|fir_top_st:fir_top_st_component|lc_tdl_strat:Utdl_0_n|sft02_n[10] at LC_X14_Y30_N8
--operation mode is normal