lockit.fit.rpt

Altera FPGA CPLD设计高级篇电子书籍

; Auto Packed Registers -- Stratix/Stratix GX                                                                ; Normal                         ; Normal                         ;
; Auto Global Memory Control Signals                                                                         ; Off                            ; Off                            ;
; Enable Bus-Hold Circuitry                                                                                  ; Off                            ; Off                            ;
; Weak Pull-Up Resistor                                                                                      ; Off                            ; Off                            ;
; PCI I/O                                                                                                    ; Off                            ; Off                            ;
; Slow Slew Rate                                                                                             ; Off                            ; Off                            ;
; Fitter Initial Placement Seed                                                                              ; 1                              ; 1                              ;
; Final Placement Optimizations                                                                              ; Automatically                  ; Automatically                  ;
; FIT_ONLY_ONE_ATTEMPT                                                                                       ; Off                            ; Off                            ;
; Optimize IOC Register Placement for Timing                                                                 ; On                             ; On                             ;
; Optimize Timing                                                                                            ; Normal Compilation             ; Normal Compilation             ;
; Optimize Hold Timing                                                                                       ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
+------------------------------------------------------------------------------------------------------------+--------------------------------+--------------------------------+


+-------------------------------------------------------------------------+
; Fitter Device Options                                                   ;
+--------------------------------------------------------------------------
; Option                                       ; Setting                  ;
+----------------------------------------------+--------------------------+
; Auto-restart configuration after error       ; On                       ;
; Release clears before tri-states             ; Off                      ;
; Enable user-supplied start-up clock (CLKUSR) ; Off                      ;
; Enable device-wide reset (DEV_CLRn)          ; Off                      ;
; Enable device-wide output enable (DEV_OE)    ; Off                      ;
; Enable INIT_DONE output                      ; Off                      ;
; Reserve all unused pins                      ; As output driving ground ;
; Base pin-out file on sameframe device        ; Off                      ;
+----------------------------------------------+--------------------------+


+-------------------+
; Fitter Equations  ;
+-------------------+
The equations can be found in D:/prj_D/LogicLock/LogicLock/lockit.fit.eqn.


+-----------------+
; Floorplan View  ;
+-----------------+
Floorplan report data cannot be output to ASCII.
Please use Quartus II to view the floorplan report data.


+---------------+
; Pin-Out File  ;
+---------------+
The pin-out file can be found in D:/prj_D/LogicLock/LogicLock/lockit.pin.


+----------------------------------------------------------+
; Fitter Resource Usage Summary                            ;
+-----------------------------------------------------------
; Resource                    ; Usage                      ;
+-----------------------------+----------------------------+
; Logic cells                 ; 1,388 / 10,570 ( 13 % )    ;
; Registers                   ; 1,362 / 12,566 ( 10 % )    ;
; Total LABs                  ; 144 / 1,057 ( 13 % )       ;
; Logic cells in carry chains ; 163                        ;
; User inserted logic cells   ; 0                          ;
; I/O pins                    ; 105 / 346 ( 30 % )         ;
;     -- Clock pins           ; 7 / 16 ( 43 % )            ;
; Global signals              ; 3                          ;
; M512s                       ; 0 / 94 ( 0 % )             ;
; M4Ks                        ; 22 / 60 ( 36 % )           ;
; M-RAMs                      ; 0 / 1 ( 0 % )              ;
; Total memory bits           ; 79,040 / 920,448 ( 8 % )   ;
; Total RAM block bits        ; 101,376 / 920,448 ( 11 % ) ;
; DSP block 9-bit elements    ; 0 / 48 ( 0 % )             ;
; Global clocks               ; 3 / 16 ( 18 % )            ;
; Regional clocks             ; 0 / 16 ( 0 % )             ;
; Fast regional clocks        ; 0 / 8 ( 0 % )              ;
; DIFFIOCLKs                  ; 0 / 16 ( 0 % )             ;
; SERDES transmitters         ; 0 / 44 ( 0 % )             ;
; SERDES receivers            ; 0 / 44 ( 0 % )             ;
; Maximum fan-out node        ; fir_clock                  ;
; Maximum fan-out             ; 1326                       ;
; Total fan-out               ; 4199                       ;
; Average fan-out             ; 2.77                       ;
+-----------------------------+----------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; LogicLock Region Resource Usage                                                                                                                                                                                                                ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
; LogicLock Region          ; Origin  ; Width ; Height ; Logic Cells ; Registers ; Memory Bits   ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins  ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ;
+---------------------------+---------+-------+--------+-------------+-----------+---------------+--------------+---------+-----------+-----------+-------+--------------+--------------+-------------------+------------------+-----------------+
; data_buffer:inst|fir_lock ; X16_Y2  ; 2     ; 16     ; 64 (64)     ; 42 (42)   ; 65536 (65536) ; 0 (0)        ; 0 (0)   ; 0 (0)     ; 0 (0)     ; 0 (0) ; 0 (0)        ; 22 (22)      ; 1 (1)             ; 41 (41)          ; 39 (39)         ;
; fir_top:inst1|fir_lock    ; X32_Y22 ; 10    ; 9      ; 662 (662)   ; 660 (660) ; 6752 (6752)   ; 0 (0)        ; 0 (0)   ; 0 (0)     ; 0 (0)     ; 0 (0) ; 0 (0)        ; 2 (2)        ; 549 (549)         ; 111 (111)        ; 62 (62)         ;
; fir_top:inst2|fir_lock    ; X12_Y21 ; 10    ; 10     ; 662 (662)   ; 660 (660) ; 6752 (6752)   ; 0 (0)        ; 0 (0)   ; 0 (0)     ; 0 (0)     ; 0 (0) ; 0 (0)        ; 2 (2)        ; 549 (549)         ; 111 (111)        ; 62 (62)         ;
+---------------------------+---------+-------+--------+-------------+-----------+---------------+--------------+---------+-----------+-----------+-------+--------------+--------------+-------------------+------------------+-----------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins                                                                                                                                                                                                                                                           ;