lockit.fit.rpt

Altera FPGA CPLD设计高级篇电子书籍

Fitter report for lockit
Wed Dec 15 04:59:23 2004
Version 4.0 Build 190 1/28/2004 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Fitter Summary
  3. Fitter Settings
  4. Fitter Device Options
  5. Fitter Equations
  6. Floorplan View
  7. Pin-Out File
  8. Fitter Resource Usage Summary
  9. LogicLock Region Resource Usage
 10. Input Pins
 11. Output Pins
 12. I/O Bank Usage
 13. All Package Pins
 14. Output Pin Load For Reported TCO
 15. Fitter Resource Utilization by Entity
 16. Delay Chain Summary
 17. Pad To Core Delay Chain Fanout
 18. Control Signals
 19. Global & Other Fast Signals
 20. Non-Global High Fan-Out Signals
 21. Fitter RAM Summary
 22. Interconnect Usage Summary
 23. LAB Logic Elements
 24. LAB-wide Signals
 25. LAB Signals Sourced
 26. LAB Signals Sourced Out
 27. LAB Distinct Inputs
 28. Fitter Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2004 Altera Corporation
Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
support information,  device programming or simulation file,  and any other
associated  documentation or information  provided by  Altera  or a partner
under  Altera's   Megafunction   Partnership   Program  may  be  used  only
to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
other  use  of such  megafunction  design,  netlist,  support  information,
device programming or simulation file,  or any other  related documentation
or information  is prohibited  for  any  other purpose,  including, but not
limited to  modification,  reverse engineering,  de-compiling, or use  with
any other  silicon devices,  unless such use is  explicitly  licensed under
a separate agreement with  Altera  or a megafunction partner.  Title to the
intellectual property,  including patents,  copyrights,  trademarks,  trade
secrets,  or maskworks,  embodied in any such megafunction design, netlist,
support  information,  device programming or simulation file,  or any other
related documentation or information provided by  Altera  or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.



+------------------------------------------------------------------+
; Fitter Summary                                                   ;
+--------------------------+---------------------------------------+
; Fitter Status            ; Successful - Wed Dec 15 04:59:23 2004 ;
; Revision Name            ; lockit                                ;
; Top-level Entity Name    ; lockit                                ;
; Family                   ; Stratix                               ;
; Device                   ; EP1S10B672C6                          ;
; Total logic elements     ; 1,388 / 10,570 ( 13 % )               ;
; Total pins               ; 105 / 346 ( 30 % )                    ;
; Total memory bits        ; 79,040 / 920,448 ( 8 % )              ;
; DSP block 9-bit elements ; 0 / 48 ( 0 % )                        ;
; Total PLLs               ; 0 / 6 ( 0 % )                         ;
; Total DLLs               ; 0 / 2 ( 0 % )                         ;
+--------------------------+---------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Settings                                                                                                                                                              ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
; Option                                                                                                     ; Setting                        ; Default Value                  ;
+------------------------------------------------------------------------------------------------------------+--------------------------------+--------------------------------+
; Device                                                                                                     ; EP1S10B672C6                   ;                                ;
; Auto Register Duplication                                                                                  ; Off                            ; Off                            ;
; Logic Cell Insertion -- Logic Duplication                                                                  ; Auto                           ; Auto                           ;
; Perform physical synthesis with extra effort; uses extra compile time to try for extra circuit performance ; Off                            ; Off                            ;
; Perform Register Retiming                                                                                  ; Off                            ; Off                            ;
; Perform Register Duplication                                                                               ; Off                            ; Off                            ;
; Perform Physical Synthesis for Combinational Logic                                                         ; Off                            ; Off                            ;
; Auto Merge PLLs                                                                                            ; On                             ; On                             ;
; Auto Delay Chains                                                                                          ; On                             ; On                             ;