data_buffer.tan.rpt

Altera FPGA CPLD设计高级篇电子书籍

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+----------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                               ;
+-----------------------------------------------------------------------------------------
; Option                                                ; Setting            ; From ; To ;
+-------------------------------------------------------+--------------------+------+----+
; Device name                                           ; EP1S10B672C6       ;      ;    ;
; Report IO Paths Separately                            ; Off                ;      ;    ;
; Ignore user-defined clock settings                    ; Off                ;      ;    ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;
; Cut off clear and preset signal paths                 ; On                 ;      ;    ;
; Cut off read during write signal paths                ; On                 ;      ;    ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;
; Run Minimum Analysis                                  ; On                 ;      ;    ;
; Use Minimum Timing Models                             ; Off                ;      ;    ;
; Number of paths to report                             ; 200                ;      ;    ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;
+-------------------------------------------------------+--------------------+------+----+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                          ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
; Type                   ; Slack ; Required Time ; Actual Time                      ; From                                                                                                                                                 ; To                                                                                                                                                    ;
+------------------------+-------+---------------+----------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Worst-case tsu         ; N/A   ; None          ; 5.987 ns                         ; rdreq                                                                                                                                                ; scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|ram_block2a15~portb_address_reg11 ;
; Worst-case tco         ; N/A   ; None          ; 13.677 ns                        ; scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|ram_block2a9~portb_address_reg11 ; q[1]                                                                                                                                                  ;
; Worst-case th          ; N/A   ; None          ; -2.689 ns                        ; data[3]                                                                                                                                              ; scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|ram_block2a3~porta_datain_reg0    ;
; Worst-case minimum tco ; N/A   ; None          ; 8.111 ns                         ; scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|b_non_empty                                            ; empty                                                                                                                                                 ;
; Clock Setup: 'clock'   ; N/A   ; None          ; 250.75 MHz ( period = 3.988 ns ) ; scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|b_full                                                 ; scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|ram_block2a3~porta_we_reg         ;
+------------------------+-------+---------------+----------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------+