data_buffer.tan.qmsg

Altera FPGA CPLD设计高级篇电子书籍

{ "Info" "ITDB_FULL_TCO_RESULT" "clock q\[1\] scfifo:scfifo_component\|scfifo_39m:auto_generated\|a_dpfifo_ihi:dpfifo\|dpram_btj:FIFOram\|altsyncram_9kb1:altsyncram1\|ram_block2a9~portb_address_reg0 13.677 ns memory " "Info: tco from clock clock to destination pin q\[1\] through memory scfifo:scfifo_component\|scfifo_39m:auto_generated\|a_dpfifo_ihi:dpfifo\|dpram_btj:FIFOram\|altsyncram_9kb1:altsyncram1\|ram_block2a9~portb_address_reg0 is 13.677 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 2.985 ns + Longest memory " "Info: + Longest clock path from clock clock to source memory is 2.985 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.662 ns) 0.662 ns clock 1 CLK Pin_M24 474 " "Info: 1: + IC(0.000 ns) + CELL(0.662 ns) = 0.662 ns; Loc. = Pin_M24; Fanout = 474; CLK Node = 'clock'" {  } { { "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" "" "" { Report "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" Compiler "data_buffer" "UNKNOWN" "V1" "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer.quartus_db" { Floorplan "" "" "" { clock } "NODE_NAME" } } } { "D:/prj_D/LogicLock/LogicLock/data_buffer/data_buffer.v" "" "" { Text "D:/prj_D/LogicLock/LogicLock/data_buffer/data_buffer.v" 49 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.755 ns) + CELL(0.568 ns) 2.985 ns scfifo:scfifo_component\|scfifo_39m:auto_generated\|a_dpfifo_ihi:dpfifo\|dpram_btj:FIFOram\|altsyncram_9kb1:altsyncram1\|ram_block2a9~portb_address_reg0 2 MEM M4K_X15_Y13 1 " "Info: 2: + IC(1.755 ns) + CELL(0.568 ns) = 2.985 ns; Loc. = M4K_X15_Y13; Fanout = 1; MEM Node = 'scfifo:scfifo_component\|scfifo_39m:auto_generated\|a_dpfifo_ihi:dpfifo\|dpram_btj:FIFOram\|altsyncram_9kb1:altsyncram1\|ram_block2a9~portb_address_reg0'" {  } { { "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" "" "" { Report "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" Compiler "data_buffer" "UNKNOWN" "V1" "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer.quartus_db" { Floorplan "" "" "2.323 ns" { clock scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|ram_block2a9~portb_address_reg0 } "NODE_NAME" } } } { "D:/prj_D/LogicLock/LogicLock/data_buffer/db/altsyncram_9kb1.tdf" "" "" { Text "D:/prj_D/LogicLock/LogicLock/data_buffer/db/altsyncram_9kb1.tdf" 311 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.230 ns 41.21 % " "Info: Total cell delay = 1.230 ns ( 41.21 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.755 ns 58.79 % " "Info: Total interconnect delay = 1.755 ns ( 58.79 % )" {  } {  } 0}  } { { "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" "" "" { Report "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" Compiler "data_buffer" "UNKNOWN" "V1" "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer.quartus_db" { Floorplan "" "" "2.985 ns" { clock scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|ram_block2a9~portb_address_reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.467 ns + " "Info: + Micro clock to output delay of source is 0.467 ns" {  } { { "D:/prj_D/LogicLock/LogicLock/data_buffer/db/altsyncram_9kb1.tdf" "" "" { Text "D:/prj_D/LogicLock/LogicLock/data_buffer/db/altsyncram_9kb1.tdf" 311 2 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.225 ns + Longest memory pin " "Info: + Longest memory to pin delay is 10.225 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns scfifo:scfifo_component\|scfifo_39m:auto_generated\|a_dpfifo_ihi:dpfifo\|dpram_btj:FIFOram\|altsyncram_9kb1:altsyncram1\|ram_block2a9~portb_address_reg0 1 MEM M4K_X15_Y13 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X15_Y13; Fanout = 1; MEM Node = 'scfifo:scfifo_component\|scfifo_39m:auto_generated\|a_dpfifo_ihi:dpfifo\|dpram_btj:FIFOram\|altsyncram_9kb1:altsyncram1\|ram_block2a9~portb_address_reg0'" {  } { { "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" "" "" { Report "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" Compiler "data_buffer" "UNKNOWN" "V1" "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer.quartus_db" { Floorplan "" "" "" { scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|ram_block2a9~portb_address_reg0 } "NODE_NAME" } } } { "D:/prj_D/LogicLock/LogicLock/data_buffer/db/altsyncram_9kb1.tdf" "" "" { Text "D:/prj_D/LogicLock/LogicLock/data_buffer/db/altsyncram_9kb1.tdf" 311 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.496 ns) 3.496 ns scfifo:scfifo_component\|scfifo_39m:auto_generated\|a_dpfifo_ihi:dpfifo\|dpram_btj:FIFOram\|altsyncram_9kb1:altsyncram1\|ram_block2a9 2 MEM M4K_X15_Y13 1 " "Info: 2: + IC(0.000 ns) + CELL(3.496 ns) = 3.496 ns; Loc. = M4K_X15_Y13; Fanout = 1; MEM Node = 'scfifo:scfifo_component\|scfifo_39m:auto_generated\|a_dpfifo_ihi:dpfifo\|dpram_btj:FIFOram\|altsyncram_9kb1:altsyncram1\|ram_block2a9'" {  } { { "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" "" "" { Report "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" Compiler "data_buffer" "UNKNOWN" "V1" "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer.quartus_db" { Floorplan "" "" "3.496 ns" { scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|ram_block2a9~portb_address_reg0 scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|ram_block2a9 } "NODE_NAME" } } } { "D:/prj_D/LogicLock/LogicLock/data_buffer/db/altsyncram_9kb1.tdf" "" "" { Text "D:/prj_D/LogicLock/LogicLock/data_buffer/db/altsyncram_9kb1.tdf" 311 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.915 ns) + CELL(0.459 ns) 5.870 ns scfifo:scfifo_component\|scfifo_39m:auto_generated\|a_dpfifo_ihi:dpfifo\|dpram_btj:FIFOram\|altsyncram_9kb1:altsyncram1\|mux_kl7:mux4\|w_result327w~10 3 COMB LC_X17_Y25_N2 1 " "Info: 3: + IC(1.915 ns) + CELL(0.459 ns) = 5.870 ns; Loc. = LC_X17_Y25_N2; Fanout = 1; COMB Node = 'scfifo:scfifo_component\|scfifo_39m:auto_generated\|a_dpfifo_ihi:dpfifo\|dpram_btj:FIFOram\|altsyncram_9kb1:altsyncram1\|mux_kl7:mux4\|w_result327w~10'" {  } { { "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" "" "" { Report "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" Compiler "data_buffer" "UNKNOWN" "V1" "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer.quartus_db" { Floorplan "" "" "2.374 ns" { scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|ram_block2a9 scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|mux_kl7:mux4|w_result327w~10 } "NODE_NAME" } } } { "D:/prj_D/LogicLock/LogicLock/data_buffer/db/mux_kl7.tdf" "" "" { Text "D:/prj_D/LogicLock/LogicLock/data_buffer/db/mux_kl7.tdf" 48 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.597 ns) + CELL(2.758 ns) 10.225 ns q\[1\] 4 PIN Pin_G11 0 " "Info: 4: + IC(1.597 ns) + CELL(2.758 ns) = 10.225 ns; Loc. = Pin_G11; Fanout = 0; PIN Node = 'q\[1\]'" {  } { { "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" "" "" { Report "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" Compiler "data_buffer" "UNKNOWN" "V1" "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer.quartus_db" { Floorplan "" "" "4.355 ns" { scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|mux_kl7:mux4|w_result327w~10 q[1] } "NODE_NAME" } } } { "D:/prj_D/LogicLock/LogicLock/data_buffer/data_buffer.v" "" "" { Text "D:/prj_D/LogicLock/LogicLock/data_buffer/data_buffer.v" 50 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.713 ns 65.65 % " "Info: Total cell delay = 6.713 ns ( 65.65 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.512 ns 34.35 % " "Info: Total interconnect delay = 3.512 ns ( 34.35 % )" {  } {  } 0}  } { { "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" "" "" { Report "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" Compiler "data_buffer" "UNKNOWN" "V1" "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer.quartus_db" { Floorplan "" "" "10.225 ns" { scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|ram_block2a9~portb_address_reg0 scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|ram_block2a9 scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|mux_kl7:mux4|w_result327w~10 q[1] } "NODE_NAME" } } }  } 0}  } { { "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" "" "" { Report "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" Compiler "data_buffer" "UNKNOWN" "V1" "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer.quartus_db" { Floorplan "" "" "2.985 ns" { clock scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|ram_block2a9~portb_address_reg0 } "NODE_NAME" } } } { "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" "" "" { Report "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" Compiler "data_buffer" "UNKNOWN" "V1" "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer.quartus_db" { Floorplan "" "" "10.225 ns" { scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|ram_block2a9~portb_address_reg0 scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|ram_block2a9 scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|mux_kl7:mux4|w_result327w~10 q[1] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "scfifo:scfifo_component\|scfifo_39m:auto_generated\|a_dpfifo_ihi:dpfifo\|dpram_btj:FIFOram\|altsyncram_9kb1:altsyncram1\|ram_block2a3~porta_datain_reg0 data\[3\] clock -2.689 ns memory " "Info: th for memory scfifo:scfifo_component\|scfifo_39m:auto_generated\|a_dpfifo_ihi:dpfifo\|dpram_btj:FIFOram\|altsyncram_9kb1:altsyncram1\|ram_block2a3~porta_datain_reg0 (data pin = data\[3\], clock pin = clock) is -2.689 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.945 ns + Longest memory " "Info: + Longest clock path from clock clock to destination memory is 2.945 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.662 ns) 0.662 ns clock 1 CLK Pin_M24 474 " "Info: 1: + IC(0.000 ns) + CELL(0.662 ns) = 0.662 ns; Loc. = Pin_M24; Fanout = 474; CLK Node = 'clock'" {  } { { "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" "" "" { Report "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" Compiler "data_buffer" "UNKNOWN" "V1" "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer.quartus_db" { Floorplan "" "" "" { clock } "NODE_NAME" } } } { "D:/prj_D/LogicLock/LogicLock/data_buffer/data_buffer.v" "" "" { Text "D:/prj_D/LogicLock/LogicLock/data_buffer/data_buffer.v" 49 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.714 ns) + CELL(0.569 ns) 2.945 ns scfifo:scfifo_component\|scfifo_39m:auto_generated\|a_dpfifo_ihi:dpfifo\|dpram_btj:FIFOram\|altsyncram_9kb1:altsyncram1\|ram_block2a3~porta_datain_reg0 2 MEM M4K_X15_Y28 1 " "Info: 2: + IC(1.714 ns) + CELL(0.569 ns) = 2.945 ns; Loc. = M4K_X15_Y28; Fanout = 1; MEM Node = 'scfifo:scfifo_component\|scfifo_39m:auto_generated\|a_dpfifo_ihi:dpfifo\|dpram_btj:FIFOram\|altsyncram_9kb1:altsyncram1\|ram_block2a3~porta_datain_reg0'" {  } { { "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" "" "" { Report "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" Compiler "data_buffer" "UNKNOWN" "V1" "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer.quartus_db" { Floorplan "" "" "2.283 ns" { clock scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|ram_block2a3~porta_datain_reg0 } "NODE_NAME" } } } { "D:/prj_D/LogicLock/LogicLock/data_buffer/db/altsyncram_9kb1.tdf" "" "" { Text "D:/prj_D/LogicLock/LogicLock/data_buffer/db/altsyncram_9kb1.tdf" 137 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.231 ns 41.80 % " "Info: Total cell delay = 1.231 ns ( 41.80 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.714 ns 58.20 % " "Info: Total interconnect delay = 1.714 ns ( 58.20 % )" {  } {  } 0}  } { { "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" "" "" { Report "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" Compiler "data_buffer" "UNKNOWN" "V1" "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer.quartus_db" { Floorplan "" "" "2.945 ns" { clock scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|ram_block2a3~porta_datain_reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.038 ns + " "Info: + Micro hold delay of destination is 0.038 ns" {  } { { "D:/prj_D/LogicLock/LogicLock/data_buffer/db/altsyncram_9kb1.tdf" "" "" { Text "D:/prj_D/LogicLock/LogicLock/data_buffer/db/altsyncram_9kb1.tdf" 137 2 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.672 ns - Shortest pin memory " "Info: - Shortest pin to memory delay is 5.672 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.976 ns) 0.976 ns data\[3\] 1 PIN Pin_E10 2 " "Info: 1: + IC(0.000 ns) + CELL(0.976 ns) = 0.976 ns; Loc. = Pin_E10; Fanout = 2; PIN Node = 'data\[3\]'" {  } { { "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" "" "" { Report "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" Compiler "data_buffer" "UNKNOWN" "V1" "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer.quartus_db" { Floorplan "" "" "" { data[3] } "NODE_NAME" } } } { "D:/prj_D/LogicLock/LogicLock/data_buffer/data_buffer.v" "" "" { Text "D:/prj_D/LogicLock/LogicLock/data_buffer/data_buffer.v" 46 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.425 ns) + CELL(0.271 ns) 5.672 ns scfifo:scfifo_component\|scfifo_39m:auto_generated\|a_dpfifo_ihi:dpfifo\|dpram_btj:FIFOram\|altsyncram_9kb1:altsyncram1\|ram_block2a3~porta_datain_reg0 2 MEM M4K_X15_Y28 1 " "Info: 2: + IC(4.425 ns) + CELL(0.271 ns) = 5.672 ns; Loc. = M4K_X15_Y28; Fanout = 1; MEM Node = 'scfifo:scfifo_component\|scfifo_39m:auto_generated\|a_dpfifo_ihi:dpfifo\|dpram_btj:FIFOram\|altsyncram_9kb1:altsyncram1\|ram_block2a3~porta_datain_reg0'" {  } { { "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" "" "" { Report "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" Compiler "data_buffer" "UNKNOWN" "V1" "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer.quartus_db" { Floorplan "" "" "4.696 ns" { data[3] scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|ram_block2a3~porta_datain_reg0 } "NODE_NAME" } } } { "D:/prj_D/LogicLock/LogicLock/data_buffer/db/altsyncram_9kb1.tdf" "" "" { Text "D:/prj_D/LogicLock/LogicLock/data_buffer/db/altsyncram_9kb1.tdf" 137 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.247 ns 21.99 % " "Info: Total cell delay = 1.247 ns ( 21.99 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.425 ns 78.01 % " "Info: Total interconnect delay = 4.425 ns ( 78.01 % )" {  } {  } 0}  } { { "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" "" "" { Report "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" Compiler "data_buffer" "UNKNOWN" "V1" "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer.quartus_db" { Floorplan "" "" "5.672 ns" { data[3] scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|ram_block2a3~porta_datain_reg0 } "NODE_NAME" } } }  } 0}  } { { "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" "" "" { Report "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" Compiler "data_buffer" "UNKNOWN" "V1" "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer.quartus_db" { Floorplan "" "" "2.945 ns" { clock scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|ram_block2a3~porta_datain_reg0 } "NODE_NAME" } } } { "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" "" "" { Report "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" Compiler "data_buffer" "UNKNOWN" "V1" "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer.quartus_db" { Floorplan "" "" "5.672 ns" { data[3] scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|ram_block2a3~porta_datain_reg0 } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "clock empty scfifo:scfifo_component\|scfifo_39m:auto_generated\|a_dpfifo_ihi:dpfifo\|a_fefifo_n4f:fifo_state\|b_non_empty 8.111 ns register " "Info: Minimum tco from clock clock to destination pin empty through register scfifo:scfifo_component\|scfifo_39m:auto_generated\|a_dpfifo_ihi:dpfifo\|a_fefifo_n4f:fifo_state\|b_non_empty is 8.111 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 3.000 ns + Shortest register " "Info: + Shortest clock path from clock clock to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.662 ns) 0.662 ns clock 1 CLK Pin_M24 474 " "Info: 1: + IC(0.000 ns) + CELL(0.662 ns) = 0.662 ns; Loc. = Pin_M24; Fanout = 474; CLK Node = 'clock'" {  } { { "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" "" "" { Report "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" Compiler "data_buffer" "UNKNOWN" "V1" "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer.quartus_db" { Floorplan "" "" "" { clock } "NODE_NAME" } } } { "D:/prj_D/LogicLock/LogicLock/data_buffer/data_buffer.v" "" "" { Text "D:/prj_D/LogicLock/LogicLock/data_buffer/data_buffer.v" 49 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.778 ns) + CELL(0.560 ns) 3.000 ns scfifo:scfifo_component\|scfifo_39m:auto_generated\|a_dpfifo_ihi:dpfifo\|a_fefifo_n4f:fifo_state\|b_non_empty 2 REG LC_X17_Y17_N2 5 " "Info: 2: + IC(1.778 ns) + CELL(0.560 ns) = 3.000 ns; Loc. = LC_X17_Y17_N2; Fanout = 5; REG Node = 'scfifo:scfifo_component\|scfifo_39m:auto_generated\|a_dpfifo_ihi:dpfifo\|a_fefifo_n4f:fifo_state\|b_non_empty'" {  } { { "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" "" "" { Report "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" Compiler "data_buffer" "UNKNOWN" "V1" "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer.quartus_db" { Floorplan "" "" "2.338 ns" { clock scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|b_non_empty } "NODE_NAME" } } } { "D:/prj_D/LogicLock/LogicLock/data_buffer/db/a_fefifo_n4f.tdf" "" "" { Text "D:/prj_D/LogicLock/LogicLock/data_buffer/db/a_fefifo_n4f.tdf" 44 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.222 ns 40.73 % " "Info: Total cell delay = 1.222 ns ( 40.73 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.778 ns 59.27 % " "Info: Total interconnect delay = 1.778 ns ( 59.27 % )" {  } {  } 0}  } { { "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" "" "" { Report "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" Compiler "data_buffer" "UNKNOWN" "V1" "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer.quartus_db" { Floorplan "" "" "3.000 ns" { clock scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|b_non_empty } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.176 ns + " "Info: + Micro clock to output delay of source is 0.176 ns" {  } { { "D:/prj_D/LogicLock/LogicLock/data_buffer/db/a_fefifo_n4f.tdf" "" "" { Text "D:/prj_D/LogicLock/LogicLock/data_buffer/db/a_fefifo_n4f.tdf" 44 2 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.935 ns + Shortest register pin " "Info: + Shortest register to pin delay is 4.935 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns scfifo:scfifo_component\|scfifo_39m:auto_generated\|a_dpfifo_ihi:dpfifo\|a_fefifo_n4f:fifo_state\|b_non_empty 1 REG LC_X17_Y17_N2 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X17_Y17_N2; Fanout = 5; REG Node = 'scfifo:scfifo_component\|scfifo_39m:auto_generated\|a_dpfifo_ihi:dpfifo\|a_fefifo_n4f:fifo_state\|b_non_empty'" {  } { { "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" "" "" { Report "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" Compiler "data_buffer" "UNKNOWN" "V1" "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer.quartus_db" { Floorplan "" "" "" { scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|b_non_empty } "NODE_NAME" } } } { "D:/prj_D/LogicLock/LogicLock/data_buffer/db/a_fefifo_n4f.tdf" "" "" { Text "D:/prj_D/LogicLock/LogicLock/data_buffer/db/a_fefifo_n4f.tdf" 44 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.177 ns) + CELL(2.758 ns) 4.935 ns empty 2 PIN Pin_AA10 0 " "Info: 2: + IC(2.177 ns) + CELL(2.758 ns) = 4.935 ns; Loc. = Pin_AA10; Fanout = 0; PIN Node = 'empty'" {  } { { "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" "" "" { Report "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" Compiler "data_buffer" "UNKNOWN" "V1" "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer.quartus_db" { Floorplan "" "" "4.935 ns" { scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|b_non_empty empty } "NODE_NAME" } } } { "D:/prj_D/LogicLock/LogicLock/data_buffer/data_buffer.v" "" "" { Text "D:/prj_D/LogicLock/LogicLock/data_buffer/data_buffer.v" 52 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.758 ns 55.89 % " "Info: Total cell delay = 2.758 ns ( 55.89 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.177 ns 44.11 % " "Info: Total interconnect delay = 2.177 ns ( 44.11 % )" {  } {  } 0}  } { { "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" "" "" { Report "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" Compiler "data_buffer" "UNKNOWN" "V1" "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer.quartus_db" { Floorplan "" "" "4.935 ns" { scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|b_non_empty empty } "NODE_NAME" } } }  } 0}  } { { "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" "" "" { Report "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" Compiler "data_buffer" "UNKNOWN" "V1" "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer.quartus_db" { Floorplan "" "" "3.000 ns" { clock scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|b_non_empty } "NODE_NAME" } } } { "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" "" "" { Report "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" Compiler "data_buffer" "UNKNOWN" "V1" "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer.quartus_db" { Floorplan "" "" "4.935 ns" { scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|b_non_empty empty } "NODE_NAME" } } }  } 0}