decode_4r6.tdf

Altera FPGA CPLD设计高级篇电子书籍

--lpm_decode DEVICE_FAMILY=Stratix LPM_DECODES=2 LPM_WIDTH=1 data enable eq
--VERSION_BEGIN 4.0 cbx_lpm_compare 2003:09:10:10:27:44:SJ cbx_lpm_decode 2003:03:25:17:43:04:SJ cbx_mgl 2004:01:13:14:00:54:SJ  VERSION_END


--  Copyright (C) 1988-2004 Altera Corporation
--  Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
--  support information,  device programming or simulation file,  and any other
--  associated  documentation or information  provided by  Altera  or a partner
--  under  Altera's   Megafunction   Partnership   Program  may  be  used  only
--  to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
--  other  use  of such  megafunction  design,  netlist,  support  information,
--  device programming or simulation file,  or any other  related documentation
--  or information  is prohibited  for  any  other purpose,  including, but not
--  limited to  modification,  reverse engineering,  de-compiling, or use  with
--  any other  silicon devices,  unless such use is  explicitly  licensed under
--  a separate agreement with  Altera  or a megafunction partner.  Title to the
--  intellectual property,  including patents,  copyrights,  trademarks,  trade
--  secrets,  or maskworks,  embodied in any such megafunction design, netlist,
--  support  information,  device programming or simulation file,  or any other
--  related documentation or information provided by  Altera  or a megafunction
--  partner, remains with Altera, the megafunction partner, or their respective
--  licensors. No other licenses, including any licenses needed under any third
--  party's intellectual property, are provided herein.



--synthesis_resources = lut 1 
SUBDESIGN decode_4r6
( 
	data[0..0]	:	input;
	enable	:	input;
	eq[1..0]	:	output;
) 
VARIABLE 
	eq_node[1..0]	: WIRE;

BEGIN 
	eq[] = eq_node[];
	eq_node[] = ( (data[] & enable), ((! data[]) & enable));
END;
--VALID FILE