data_buffer.cdb.qmsg

Altera FPGA CPLD设计高级篇电子书籍

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Compiler Database Interface " "Info: Running Quartus II Compiler Database Interface" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.0 Build 190 1/28/2004 SJ Full Version " "Info: Version 4.0 Build 190 1/28/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Dec 15 03:48:12 2004 " "Info: Processing started: Wed Dec 15 03:48:12 2004" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_cdb data_buffer -c data_buffer --vqm=D:/prj_D/LogicLock/LogicLock/data_buffer/atom_netlists/data_buffer.vqm " "Info: Command: quartus_cdb data_buffer -c data_buffer --vqm=D:/prj_D/LogicLock/LogicLock/data_buffer/atom_netlists/data_buffer.vqm" {  } {  } 0}
{ "Info" "IBASEO_GENERATE_LOGICLOCK_FILES_FOR_POSTFIT_NETLIST" "" "Info: VQM is being generated using the Post-Fitter Netlist." {  } {  } 0}
{ "Info" "IQATM_GENERATED_VQM_FILE" "D:/prj_D/LogicLock/LogicLock/data_buffer/atom_netlists/data_buffer.vqm " "Info: Generated Verilog Quartus Mapping File D:/prj_D/LogicLock/LogicLock/data_buffer/atom_netlists/data_buffer.vqm" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Compiler Database Interface 0 s 0 s " "Info: Quartus II Compiler Database Interface was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Dec 15 03:48:13 2004 " "Info: Processing ended: Wed Dec 15 03:48:13 2004" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0}  } {  } 0}