data_buffer.fit.qmsg

Altera FPGA CPLD设计高级篇电子书籍

{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "3.284 ns memory memory " "Info: Estimated most critical path is memory to memory delay of 3.284 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns scfifo:scfifo_component\|scfifo_39m:auto_generated\|a_dpfifo_ihi:dpfifo\|dpram_btj:FIFOram\|altsyncram_9kb1:altsyncram1\|ram_block2a0~porta_datain_reg0 1 MEM M4K_X15_Y19 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X15_Y19; Fanout = 1; MEM Node = 'scfifo:scfifo_component\|scfifo_39m:auto_generated\|a_dpfifo_ihi:dpfifo\|dpram_btj:FIFOram\|altsyncram_9kb1:altsyncram1\|ram_block2a0~porta_datain_reg0'" {  } { { "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" "" "" { Report "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" Compiler "data_buffer" "UNKNOWN" "V1" "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer.quartus_db" { Floorplan "" "" "" { scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|ram_block2a0~porta_datain_reg0 } "NODE_NAME" } } } { "D:/prj_D/LogicLock/LogicLock/data_buffer/db/altsyncram_9kb1.tdf" "" "" { Text "D:/prj_D/LogicLock/LogicLock/data_buffer/db/altsyncram_9kb1.tdf" 50 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.284 ns) 3.284 ns scfifo:scfifo_component\|scfifo_39m:auto_generated\|a_dpfifo_ihi:dpfifo\|dpram_btj:FIFOram\|altsyncram_9kb1:altsyncram1\|ram_block2a0~porta_memory_reg0 2 MEM M4K_X15_Y19 0 " "Info: 2: + IC(0.000 ns) + CELL(3.284 ns) = 3.284 ns; Loc. = M4K_X15_Y19; Fanout = 0; MEM Node = 'scfifo:scfifo_component\|scfifo_39m:auto_generated\|a_dpfifo_ihi:dpfifo\|dpram_btj:FIFOram\|altsyncram_9kb1:altsyncram1\|ram_block2a0~porta_memory_reg0'" {  } { { "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" "" "" { Report "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" Compiler "data_buffer" "UNKNOWN" "V1" "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer.quartus_db" { Floorplan "" "" "3.284 ns" { scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|ram_block2a0~porta_datain_reg0 scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|ram_block2a0~porta_memory_reg0 } "NODE_NAME" } } } { "D:/prj_D/LogicLock/LogicLock/data_buffer/db/altsyncram_9kb1.tdf" "" "" { Text "D:/prj_D/LogicLock/LogicLock/data_buffer/db/altsyncram_9kb1.tdf" 50 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.284 ns 100.00 % " "Info: Total cell delay = 3.284 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" "" "" { Report "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" Compiler "data_buffer" "UNKNOWN" "V1" "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer.quartus_db" { Floorplan "" "" "3.284 ns" { scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|ram_block2a0~porta_datain_reg0 scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|ram_block2a0~porta_memory_reg0 } "NODE_NAME" } } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PLACER_ESTIMATED_PERCENT_ROUTING_RESOURCE_USAGE" "1 " "Info: Estimated interconnect usage is 1% of the available device resources" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "1 " "Info: Fitter placement operations ending: elapsed time = 1 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "1 " "Info: Fitter routing operations ending: elapsed time = 1 seconds" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Dec 15 03:35:33 2004 " "Info: Processing ended: Wed Dec 15 03:35:33 2004" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:38 " "Info: Elapsed time: 00:00:38" {  } {  } 0}  } {  } 0}