data_buffer.csf.qmsg

Altera FPGA CPLD设计高级篇电子书籍

{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Dec 15 03:35:33 2004 " "Info: Processing ended: Wed Dec 15 03:35:33 2004" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:38 " "Info: Elapsed time: 00:00:38" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.0 Build 190 1/28/2004 SJ Full Version " "Info: Version 4.0 Build 190 1/28/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Dec 15 03:35:35 2004 " "Info: Processing started: Wed Dec 15 03:35:35 2004" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --import_settings_files=off --export_settings_files=off data_buffer -c data_buffer " "Info: Command: quartus_asm --import_settings_files=off --export_settings_files=off data_buffer -c data_buffer" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Dec 15 03:35:40 2004 " "Info: Processing ended: Wed Dec 15 03:35:40 2004" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.0 Build 190 1/28/2004 SJ Full Version " "Info: Version 4.0 Build 190 1/28/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Dec 15 03:35:42 2004 " "Info: Processing started: Wed Dec 15 03:35:42 2004" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --import_settings_files=off --export_settings_files=off data_buffer -c data_buffer --timing_analysis_only " "Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off data_buffer -c data_buffer --timing_analysis_only" {  } {  } 0}
{ "Warning" "WTDB_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITDB_NODE_MAP_TO_CLK" "clock " "Info: Assuming node clock is an undefined clock" {  } { { "D:/prj_D/LogicLock/LogicLock/data_buffer/data_buffer.v" "" "" { Text "D:/prj_D/LogicLock/LogicLock/data_buffer/data_buffer.v" 49 -1 0 } } { "c:/eda/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/eda/quartus/bin/Assignment Editor.qase" 1 { { 0 "clock" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clock register scfifo:scfifo_component\|scfifo_39m:auto_generated\|a_dpfifo_ihi:dpfifo\|a_fefifo_n4f:fifo_state\|b_full memory scfifo:scfifo_component\|scfifo_39m:auto_generated\|a_dpfifo_ihi:dpfifo\|dpram_btj:FIFOram\|altsyncram_9kb1:altsyncram1\|ram_block2a3~porta_we_reg 250.75 MHz 3.988 ns Internal " "Info: Clock clock has Internal fmax of 250.75 MHz between source register scfifo:scfifo_component\|scfifo_39m:auto_generated\|a_dpfifo_ihi:dpfifo\|a_fefifo_n4f:fifo_state\|b_full and destination memory scfifo:scfifo_component\|scfifo_39m:auto_generated\|a_dpfifo_ihi:dpfifo\|dpram_btj:FIFOram\|altsyncram_9kb1:altsyncram1\|ram_block2a3~porta_we_reg (period= 3.988 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.608 ns + Longest register memory " "Info: + Longest register to memory delay is 3.608 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns scfifo:scfifo_component\|scfifo_39m:auto_generated\|a_dpfifo_ihi:dpfifo\|a_fefifo_n4f:fifo_state\|b_full 1 REG LC_X17_Y17_N8 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X17_Y17_N8; Fanout = 7; REG Node = 'scfifo:scfifo_component\|scfifo_39m:auto_generated\|a_dpfifo_ihi:dpfifo\|a_fefifo_n4f:fifo_state\|b_full'" {  } { { "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" "" "" { Report "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" Compiler "data_buffer" "UNKNOWN" "V1" "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer.quartus_db" { Floorplan "" "" "" { scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|b_full } "NODE_NAME" } } } { "D:/prj_D/LogicLock/LogicLock/data_buffer/db/a_fefifo_n4f.tdf" "" "" { Text "D:/prj_D/LogicLock/LogicLock/data_buffer/db/a_fefifo_n4f.tdf" 43 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.283 ns) + CELL(0.087 ns) 1.370 ns scfifo:scfifo_component\|scfifo_39m:auto_generated\|a_dpfifo_ihi:dpfifo\|dpram_btj:FIFOram\|altsyncram_9kb1:altsyncram1\|decode_4r6:decode3\|eq_node\[0\]~21 2 COMB LC_X17_Y20_N9 8 " "Info: 2: + IC(1.283 ns) + CELL(0.087 ns) = 1.370 ns; Loc. = LC_X17_Y20_N9; Fanout = 8; COMB Node = 'scfifo:scfifo_component\|scfifo_39m:auto_generated\|a_dpfifo_ihi:dpfifo\|dpram_btj:FIFOram\|altsyncram_9kb1:altsyncram1\|decode_4r6:decode3\|eq_node\[0\]~21'" {  } { { "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" "" "" { Report "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" Compiler "data_buffer" "UNKNOWN" "V1" "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer.quartus_db" { Floorplan "" "" "1.370 ns" { scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|b_full scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|decode_4r6:decode3|eq_node[0]~21 } "NODE_NAME" } } } { "D:/prj_D/LogicLock/LogicLock/data_buffer/db/decode_4r6.tdf" "" "" { Text "D:/prj_D/LogicLock/LogicLock/data_buffer/db/decode_4r6.tdf" 35 9 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.908 ns) + CELL(0.330 ns) 3.608 ns scfifo:scfifo_component\|scfifo_39m:auto_generated\|a_dpfifo_ihi:dpfifo\|dpram_btj:FIFOram\|altsyncram_9kb1:altsyncram1\|ram_block2a3~porta_we_reg 3 MEM M4K_X15_Y28 0 " "Info: 3: + IC(1.908 ns) + CELL(0.330 ns) = 3.608 ns; Loc. = M4K_X15_Y28; Fanout = 0; MEM Node = 'scfifo:scfifo_component\|scfifo_39m:auto_generated\|a_dpfifo_ihi:dpfifo\|dpram_btj:FIFOram\|altsyncram_9kb1:altsyncram1\|ram_block2a3~porta_we_reg'" {  } { { "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" "" "" { Report "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" Compiler "data_buffer" "UNKNOWN" "V1" "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer.quartus_db" { Floorplan "" "" "2.238 ns" { scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|decode_4r6:decode3|eq_node[0]~21 scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|ram_block2a3~porta_we_reg } "NODE_NAME" } } } { "D:/prj_D/LogicLock/LogicLock/data_buffer/db/altsyncram_9kb1.tdf" "" "" { Text "D:/prj_D/LogicLock/LogicLock/data_buffer/db/altsyncram_9kb1.tdf" 137 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.417 ns 11.56 % " "Info: Total cell delay = 0.417 ns ( 11.56 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.191 ns 88.44 % " "Info: Total interconnect delay = 3.191 ns ( 88.44 % )" {  } {  } 0}  } { { "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" "" "" { Report "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" Compiler "data_buffer" "UNKNOWN" "V1" "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer.quartus_db" { Floorplan "" "" "3.608 ns" { scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|b_full scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|decode_4r6:decode3|eq_node[0]~21 scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|ram_block2a3~porta_we_reg } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.055 ns - Smallest " "Info: - Smallest clock skew is -0.055 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.945 ns + Shortest memory " "Info: + Shortest clock path from clock clock to destination memory is 2.945 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.662 ns) 0.662 ns clock 1 CLK Pin_M24 474 " "Info: 1: + IC(0.000 ns) + CELL(0.662 ns) = 0.662 ns; Loc. = Pin_M24; Fanout = 474; CLK Node = 'clock'" {  } { { "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" "" "" { Report "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" Compiler "data_buffer" "UNKNOWN" "V1" "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer.quartus_db" { Floorplan "" "" "" { clock } "NODE_NAME" } } } { "D:/prj_D/LogicLock/LogicLock/data_buffer/data_buffer.v" "" "" { Text "D:/prj_D/LogicLock/LogicLock/data_buffer/data_buffer.v" 49 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.714 ns) + CELL(0.569 ns) 2.945 ns scfifo:scfifo_component\|scfifo_39m:auto_generated\|a_dpfifo_ihi:dpfifo\|dpram_btj:FIFOram\|altsyncram_9kb1:altsyncram1\|ram_block2a3~porta_we_reg 2 MEM M4K_X15_Y28 0 " "Info: 2: + IC(1.714 ns) + CELL(0.569 ns) = 2.945 ns; Loc. = M4K_X15_Y28; Fanout = 0; MEM Node = 'scfifo:scfifo_component\|scfifo_39m:auto_generated\|a_dpfifo_ihi:dpfifo\|dpram_btj:FIFOram\|altsyncram_9kb1:altsyncram1\|ram_block2a3~porta_we_reg'" {  } { { "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" "" "" { Report "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" Compiler "data_buffer" "UNKNOWN" "V1" "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer.quartus_db" { Floorplan "" "" "2.283 ns" { clock scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|ram_block2a3~porta_we_reg } "NODE_NAME" } } } { "D:/prj_D/LogicLock/LogicLock/data_buffer/db/altsyncram_9kb1.tdf" "" "" { Text "D:/prj_D/LogicLock/LogicLock/data_buffer/db/altsyncram_9kb1.tdf" 137 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.231 ns 41.80 % " "Info: Total cell delay = 1.231 ns ( 41.80 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.714 ns 58.20 % " "Info: Total interconnect delay = 1.714 ns ( 58.20 % )" {  } {  } 0}  } { { "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" "" "" { Report "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" Compiler "data_buffer" "UNKNOWN" "V1" "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer.quartus_db" { Floorplan "" "" "2.945 ns" { clock scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|ram_block2a3~porta_we_reg } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 3.000 ns - Longest register " "Info: - Longest clock path from clock clock to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.662 ns) 0.662 ns clock 1 CLK Pin_M24 474 " "Info: 1: + IC(0.000 ns) + CELL(0.662 ns) = 0.662 ns; Loc. = Pin_M24; Fanout = 474; CLK Node = 'clock'" {  } { { "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" "" "" { Report "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" Compiler "data_buffer" "UNKNOWN" "V1" "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer.quartus_db" { Floorplan "" "" "" { clock } "NODE_NAME" } } } { "D:/prj_D/LogicLock/LogicLock/data_buffer/data_buffer.v" "" "" { Text "D:/prj_D/LogicLock/LogicLock/data_buffer/data_buffer.v" 49 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.778 ns) + CELL(0.560 ns) 3.000 ns scfifo:scfifo_component\|scfifo_39m:auto_generated\|a_dpfifo_ihi:dpfifo\|a_fefifo_n4f:fifo_state\|b_full 2 REG LC_X17_Y17_N8 7 " "Info: 2: + IC(1.778 ns) + CELL(0.560 ns) = 3.000 ns; Loc. = LC_X17_Y17_N8; Fanout = 7; REG Node = 'scfifo:scfifo_component\|scfifo_39m:auto_generated\|a_dpfifo_ihi:dpfifo\|a_fefifo_n4f:fifo_state\|b_full'" {  } { { "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" "" "" { Report "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" Compiler "data_buffer" "UNKNOWN" "V1" "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer.quartus_db" { Floorplan "" "" "2.338 ns" { clock scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|b_full } "NODE_NAME" } } } { "D:/prj_D/LogicLock/LogicLock/data_buffer/db/a_fefifo_n4f.tdf" "" "" { Text "D:/prj_D/LogicLock/LogicLock/data_buffer/db/a_fefifo_n4f.tdf" 43 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.222 ns 40.73 % " "Info: Total cell delay = 1.222 ns ( 40.73 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.778 ns 59.27 % " "Info: Total interconnect delay = 1.778 ns ( 59.27 % )" {  } {  } 0}  } { { "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" "" "" { Report "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" Compiler "data_buffer" "UNKNOWN" "V1" "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer.quartus_db" { Floorplan "" "" "3.000 ns" { clock scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|b_full } "NODE_NAME" } } }  } 0}  } { { "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" "" "" { Report "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" Compiler "data_buffer" "UNKNOWN" "V1" "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer.quartus_db" { Floorplan "" "" "2.945 ns" { clock scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|ram_block2a3~porta_we_reg } "NODE_NAME" } } } { "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" "" "" { Report "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" Compiler "data_buffer" "UNKNOWN" "V1" "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer.quartus_db" { Floorplan "" "" "3.000 ns" { clock scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|b_full } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.176 ns + " "Info: + Micro clock to output delay of source is 0.176 ns" {  } { { "D:/prj_D/LogicLock/LogicLock/data_buffer/db/a_fefifo_n4f.tdf" "" "" { Text "D:/prj_D/LogicLock/LogicLock/data_buffer/db/a_fefifo_n4f.tdf" 43 2 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.149 ns + " "Info: + Micro setup delay of destination is 0.149 ns" {  } { { "D:/prj_D/LogicLock/LogicLock/data_buffer/db/altsyncram_9kb1.tdf" "" "" { Text "D:/prj_D/LogicLock/LogicLock/data_buffer/db/altsyncram_9kb1.tdf" 137 2 0 } }  } 0}  } { { "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" "" "" { Report "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" Compiler "data_buffer" "UNKNOWN" "V1" "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer.quartus_db" { Floorplan "" "" "3.608 ns" { scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|b_full scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|decode_4r6:decode3|eq_node[0]~21 scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|ram_block2a3~porta_we_reg } "NODE_NAME" } } } { "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" "" "" { Report "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" Compiler "data_buffer" "UNKNOWN" "V1" "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer.quartus_db" { Floorplan "" "" "2.945 ns" { clock scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|ram_block2a3~porta_we_reg } "NODE_NAME" } } } { "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" "" "" { Report "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" Compiler "data_buffer" "UNKNOWN" "V1" "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer.quartus_db" { Floorplan "" "" "3.000 ns" { clock scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|b_full } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "scfifo:scfifo_component\|scfifo_39m:auto_generated\|a_dpfifo_ihi:dpfifo\|dpram_btj:FIFOram\|altsyncram_9kb1:altsyncram1\|ram_block2a15~portb_address_reg0 rdreq clock 5.987 ns memory " "Info: tsu for memory scfifo:scfifo_component\|scfifo_39m:auto_generated\|a_dpfifo_ihi:dpfifo\|dpram_btj:FIFOram\|altsyncram_9kb1:altsyncram1\|ram_block2a15~portb_address_reg0 (data pin = rdreq, clock pin = clock) is 5.987 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.779 ns + Longest pin memory " "Info: + Longest pin to memory delay is 8.779 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.976 ns) 0.976 ns rdreq 1 PIN Pin_G9 5 " "Info: 1: + IC(0.000 ns) + CELL(0.976 ns) = 0.976 ns; Loc. = Pin_G9; Fanout = 5; PIN Node = 'rdreq'" {  } { { "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" "" "" { Report "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" Compiler "data_buffer" "UNKNOWN" "V1" "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer.quartus_db" { Floorplan "" "" "" { rdreq } "NODE_NAME" } } } { "D:/prj_D/LogicLock/LogicLock/data_buffer/data_buffer.v" "" "" { Text "D:/prj_D/LogicLock/LogicLock/data_buffer/data_buffer.v" 48 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.725 ns) + CELL(0.459 ns) 6.160 ns scfifo:scfifo_component\|scfifo_39m:auto_generated\|a_dpfifo_ihi:dpfifo\|valid_rreq 2 COMB LC_X17_Y17_N9 206 " "Info: 2: + IC(4.725 ns) + CELL(0.459 ns) = 6.160 ns; Loc. = LC_X17_Y17_N9; Fanout = 206; COMB Node = 'scfifo:scfifo_component\|scfifo_39m:auto_generated\|a_dpfifo_ihi:dpfifo\|valid_rreq'" {  } { { "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" "" "" { Report "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" Compiler "data_buffer" "UNKNOWN" "V1" "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer.quartus_db" { Floorplan "" "" "5.184 ns" { rdreq scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|valid_rreq } "NODE_NAME" } } } { "D:/prj_D/LogicLock/LogicLock/data_buffer/db/a_dpfifo_ihi.tdf" "" "" { Text "D:/prj_D/LogicLock/LogicLock/data_buffer/db/a_dpfifo_ihi.tdf" 62 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.986 ns) + CELL(0.633 ns) 8.779 ns scfifo:scfifo_component\|scfifo_39m:auto_generated\|a_dpfifo_ihi:dpfifo\|dpram_btj:FIFOram\|altsyncram_9kb1:altsyncram1\|ram_block2a15~portb_address_reg0 3 MEM M4K_X15_Y27 1 " "Info: 3: + IC(1.986 ns) + CELL(0.633 ns) = 8.779 ns; Loc. = M4K_X15_Y27; Fanout = 1; MEM Node = 'scfifo:scfifo_component\|scfifo_39m:auto_generated\|a_dpfifo_ihi:dpfifo\|dpram_btj:FIFOram\|altsyncram_9kb1:altsyncram1\|ram_block2a15~portb_address_reg0'" {  } { { "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" "" "" { Report "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" Compiler "data_buffer" "UNKNOWN" "V1" "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer.quartus_db" { Floorplan "" "" "2.619 ns" { scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|valid_rreq scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|ram_block2a15~portb_address_reg0 } "NODE_NAME" } } } { "D:/prj_D/LogicLock/LogicLock/data_buffer/db/altsyncram_9kb1.tdf" "" "" { Text "D:/prj_D/LogicLock/LogicLock/data_buffer/db/altsyncram_9kb1.tdf" 485 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.068 ns 23.56 % " "Info: Total cell delay = 2.068 ns ( 23.56 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.711 ns 76.44 % " "Info: Total interconnect delay = 6.711 ns ( 76.44 % )" {  } {  } 0}  } { { "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" "" "" { Report "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" Compiler "data_buffer" "UNKNOWN" "V1" "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer.quartus_db" { Floorplan "" "" "8.779 ns" { rdreq scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|valid_rreq scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|ram_block2a15~portb_address_reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.149 ns + " "Info: + Micro setup delay of destination is 0.149 ns" {  } { { "D:/prj_D/LogicLock/LogicLock/data_buffer/db/altsyncram_9kb1.tdf" "" "" { Text "D:/prj_D/LogicLock/LogicLock/data_buffer/db/altsyncram_9kb1.tdf" 485 2 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.941 ns - Shortest memory " "Info: - Shortest clock path from clock clock to destination memory is 2.941 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.662 ns) 0.662 ns clock 1 CLK Pin_M24 474 " "Info: 1: + IC(0.000 ns) + CELL(0.662 ns) = 0.662 ns; Loc. = Pin_M24; Fanout = 474; CLK Node = 'clock'" {  } { { "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" "" "" { Report "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" Compiler "data_buffer" "UNKNOWN" "V1" "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer.quartus_db" { Floorplan "" "" "" { clock } "NODE_NAME" } } } { "D:/prj_D/LogicLock/LogicLock/data_buffer/data_buffer.v" "" "" { Text "D:/prj_D/LogicLock/LogicLock/data_buffer/data_buffer.v" 49 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.711 ns) + CELL(0.568 ns) 2.941 ns scfifo:scfifo_component\|scfifo_39m:auto_generated\|a_dpfifo_ihi:dpfifo\|dpram_btj:FIFOram\|altsyncram_9kb1:altsyncram1\|ram_block2a15~portb_address_reg0 2 MEM M4K_X15_Y27 1 " "Info: 2: + IC(1.711 ns) + CELL(0.568 ns) = 2.941 ns; Loc. = M4K_X15_Y27; Fanout = 1; MEM Node = 'scfifo:scfifo_component\|scfifo_39m:auto_generated\|a_dpfifo_ihi:dpfifo\|dpram_btj:FIFOram\|altsyncram_9kb1:altsyncram1\|ram_block2a15~portb_address_reg0'" {  } { { "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" "" "" { Report "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" Compiler "data_buffer" "UNKNOWN" "V1" "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer.quartus_db" { Floorplan "" "" "2.279 ns" { clock scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|ram_block2a15~portb_address_reg0 } "NODE_NAME" } } } { "D:/prj_D/LogicLock/LogicLock/data_buffer/db/altsyncram_9kb1.tdf" "" "" { Text "D:/prj_D/LogicLock/LogicLock/data_buffer/db/altsyncram_9kb1.tdf" 485 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.230 ns 41.82 % " "Info: Total cell delay = 1.230 ns ( 41.82 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.711 ns 58.18 % " "Info: Total interconnect delay = 1.711 ns ( 58.18 % )" {  } {  } 0}  } { { "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" "" "" { Report "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" Compiler "data_buffer" "UNKNOWN" "V1" "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer.quartus_db" { Floorplan "" "" "2.941 ns" { clock scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|ram_block2a15~portb_address_reg0 } "NODE_NAME" } } }  } 0}  } { { "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" "" "" { Report "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" Compiler "data_buffer" "UNKNOWN" "V1" "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer.quartus_db" { Floorplan "" "" "8.779 ns" { rdreq scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|valid_rreq scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|ram_block2a15~portb_address_reg0 } "NODE_NAME" } } } { "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" "" "" { Report "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" Compiler "data_buffer" "UNKNOWN" "V1" "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer.quartus_db" { Floorplan "" "" "2.941 ns" { clock scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|ram_block2a15~portb_address_reg0 } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clock q\[1\] scfifo:scfifo_component\|scfifo_39m:auto_generated\|a_dpfifo_ihi:dpfifo\|dpram_btj:FIFOram\|altsyncram_9kb1:altsyncram1\|ram_block2a9~portb_address_reg0 13.677 ns memory " "Info: tco from clock clock to destination pin q\[1\] through memory scfifo:scfifo_component\|scfifo_39m:auto_generated\|a_dpfifo_ihi:dpfifo\|dpram_btj:FIFOram\|altsyncram_9kb1:altsyncram1\|ram_block2a9~portb_address_reg0 is 13.677 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 2.985 ns + Longest memory " "Info: + Longest clock path from clock clock to source memory is 2.985 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.662 ns) 0.662 ns clock 1 CLK Pin_M24 474 " "Info: 1: + IC(0.000 ns) + CELL(0.662 ns) = 0.662 ns; Loc. = Pin_M24; Fanout = 474; CLK Node = 'clock'" {  } { { "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" "" "" { Report "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer_cmp.qrpt" Compiler "data_buffer" "UNKNOWN" "V1" "D:/prj_D/LogicLock/LogicLock/data_buffer/db/data_buffer.quartus_db" { Floorplan "" "" "" { clock } "NODE_NAME" } } } { "D:/prj_D/LogicLock/LogicLock/data_buffer/data_buffer.v" "" "" { Text "D:/prj_D/LogicLock/LogicLock/data_buffer/data_buffer.v" 49 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.755 ns) + CELL(0.568 ns) 2.985 ns scfifo:scfifo_component\|scfifo_39m:auto_generated\|a_dpfifo_ihi:dpfifo\|dpram_btj:FIFOram\|al