📄 data_buffer.map.rpt
字号:
; Compilation Hierarchy Node ; Logic Cells ; Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name ;
+------------------------------------------------------+-------------+-----------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; |data_buffer ; 65 (0) ; 42 ; 65536 ; 0 ; 0 ; 0 ; 0 ; 21 ; 0 ; 23 (0) ; 1 (0) ; 41 (0) ; 39 (0) ; |data_buffer ;
; |scfifo:scfifo_component| ; 65 (0) ; 42 ; 65536 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 23 (0) ; 1 (0) ; 41 (0) ; 39 (0) ; |data_buffer|scfifo:scfifo_component ;
; |scfifo_39m:auto_generated| ; 65 (0) ; 42 ; 65536 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 23 (0) ; 1 (0) ; 41 (0) ; 39 (0) ; |data_buffer|scfifo:scfifo_component|scfifo_39m:auto_generated ;
; |a_dpfifo_ihi:dpfifo| ; 65 (2) ; 42 ; 65536 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 23 (2) ; 1 (0) ; 41 (0) ; 39 (0) ; |data_buffer|scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo ;
; |a_fefifo_n4f:fifo_state| ; 26 (13) ; 15 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 11 (11) ; 0 (0) ; 15 (2) ; 13 (0) ; |data_buffer|scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state ;
; |lpm_counter:count_usedw| ; 13 (0) ; 13 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 13 (0) ; 13 (0) ; |data_buffer|scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|lpm_counter:count_usedw ;
; |alt_counter_stratix:wysi_counter| ; 13 (13) ; 13 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 13 (13) ; 13 (13) ; |data_buffer|scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|lpm_counter:count_usedw|alt_counter_stratix:wysi_counter ;
; |dpram_btj:FIFOram| ; 11 (0) ; 1 ; 65536 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 10 (0) ; 1 (0) ; 0 (0) ; 0 (0) ; |data_buffer|scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram ;
; |altsyncram_9kb1:altsyncram1| ; 11 (1) ; 1 ; 65536 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 10 (0) ; 1 (1) ; 0 (0) ; 0 (0) ; |data_buffer|scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1 ;
; |decode_4r6:decode3| ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; 0 (0) ; |data_buffer|scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|decode_4r6:decode3 ;
; |mux_kl7:mux4| ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 8 (8) ; 0 (0) ; 0 (0) ; 0 (0) ; |data_buffer|scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|mux_kl7:mux4 ;
; |lpm_counter:rd_ptr_count| ; 13 (0) ; 13 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 13 (0) ; 13 (0) ; |data_buffer|scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|lpm_counter:rd_ptr_count ;
; |alt_counter_stratix:wysi_counter| ; 13 (13) ; 13 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 13 (13) ; 13 (13) ; |data_buffer|scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|lpm_counter:rd_ptr_count|alt_counter_stratix:wysi_counter ;
; |lpm_counter:wr_ptr| ; 13 (0) ; 13 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 13 (0) ; 13 (0) ; |data_buffer|scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|lpm_counter:wr_ptr ;
; |alt_counter_stratix:wysi_counter| ; 13 (13) ; 13 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 13 (13) ; 13 (13) ; |data_buffer|scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|lpm_counter:wr_ptr|alt_counter_stratix:wysi_counter ;
+------------------------------------------------------+-------------+-----------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+---------------------------------+
; Analysis & Synthesis Equations ;
+---------------------------------+
The equations can be found in D:/prj_D/LogicLock/LogicLock/data_buffer/data_buffer.map.eqn.
+------------------------------------------------------------------------+
; Analysis & Synthesis Files Read ;
+-------------------------------------------------------------------------
; File Name ; Read ;
+-----------------------------------------------------------------+------+
; D:/prj_D/LogicLock/LogicLock/data_buffer/data_buffer.v ; Read ;
; c:/eda/quartus/libraries/megafunctions/scfifo.tdf ; Read ;
; D:/prj_D/LogicLock/LogicLock/data_buffer/db/scfifo_39m.tdf ; Read ;
; D:/prj_D/LogicLock/LogicLock/data_buffer/db/a_dpfifo_ihi.tdf ; Read ;
; D:/prj_D/LogicLock/LogicLock/data_buffer/db/a_fefifo_n4f.tdf ; Read ;
; c:/eda/quartus/libraries/megafunctions/lpm_counter.tdf ; Read ;
; c:/eda/quartus/libraries/megafunctions/alt_counter_stratix.tdf ; Read ;
; D:/prj_D/LogicLock/LogicLock/data_buffer/db/dpram_btj.tdf ; Read ;
; D:/prj_D/LogicLock/LogicLock/data_buffer/db/altsyncram_9kb1.tdf ; Read ;
; D:/prj_D/LogicLock/LogicLock/data_buffer/db/decode_4r6.tdf ; Read ;
; D:/prj_D/LogicLock/LogicLock/data_buffer/db/mux_kl7.tdf ; Read ;
+-----------------------------------------------------------------+------+
+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+----------------------------------------------
; Resource ; Usage ;
+-------------------------------+-------------+
; Logic cells ; 65 ;
; Total combinational functions ; 64 ;
; Total registers ; 42 ;
; I/O pins ; 21 ;
; Total memory bits ; 65536 ;
; Maximum fan-out node ; clock ;
; Maximum fan-out ; 58 ;
; Total fan-out ; 711 ;
; Average fan-out ; 6.97 ;
+-------------------------------+-------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ;
+--------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+------+
; scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|ALTSYNCRAM ; M4K ; Simple Dual Port ; 8192 ; 8 ; 8192 ; 8 ; 65536 ; None ;
+--------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+------+
+----------------------------------------------------------------+
; WYSIWYG Cells ;
+-----------------------------------------------------------------
; Statistic ; Value ;
+--------------------------------------------------------+-------+
; Number of WYSIWYG cells ; 39 ;
; Number of synthesis-generated cells ; 26 ;
; Number of WYSIWYG LUTs ; 39 ;
; Number of synthesis-generated LUTs ; 25 ;
; Number of WYSIWYG registers ; 39 ;
; Number of synthesis-generated registers ; 3 ;
; Number of cells with combinational logic only ; 23 ;
; Number of cells with registers only ; 1 ;
; Number of cells with combinational logic and registers ; 41 ;
+--------------------------------------------------------+-------+
+----------------------------------------------+
; General Register Statistics ;
+-----------------------------------------------
; Statistic ; Value ;
+--------------------------------------+-------+
; Number of registers using SCLR ; 0 ;
; Number of registers using SLOAD ; 0 ;
; Number of registers using ACLR ; 0 ;
; Number of registers using ALOAD ; 0 ;
; Number of registers using CLK_ENABLE ; 14 ;
; Number of registers using OE ; 0 ;
; Number of registers using PRESET ; 0 ;
+--------------------------------------+-------+
+--------------------------------+
; Analysis & Synthesis Messages ;
+--------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 4.0 Build 190 1/28/2004 SJ Full Version
Info: Processing started: Wed Dec 15 03:34:47 2004
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off data_buffer -c data_buffer
Info: Using design file data_buffer.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
Info: Found entity 1: data_buffer
Info: Found 1 design units and 1 entities in source file c:/eda/quartus/libraries/megafunctions/scfifo.tdf
Info: Found entity 1: scfifo
Info: Found 1 design units and 1 entities in source file db/scfifo_39m.tdf
Info: Found entity 1: scfifo_39m
Info: Found 1 design units and 1 entities in source file db/a_dpfifo_ihi.tdf
Info: Found entity 1: a_dpfifo_ihi
Info: Found 1 design units and 1 entities in source file db/a_fefifo_n4f.tdf
Info: Found entity 1: a_fefifo_n4f
Info: Found 1 design units and 1 entities in source file c:/eda/quartus/libraries/megafunctions/lpm_counter.tdf
Info: Found entity 1: lpm_counter
Info: Found 1 design units and 1 entities in source file c:/eda/quartus/libraries/megafunctions/alt_counter_stratix.tdf
Info: Found entity 1: alt_counter_stratix
Info: Found 1 design units and 1 entities in source file db/dpram_btj.tdf
Info: Found entity 1: dpram_btj
Info: Found 1 design units and 1 entities in source file db/altsyncram_9kb1.tdf
Info: Found entity 1: altsyncram_9kb1
Info: Found 1 design units and 1 entities in source file db/decode_4r6.tdf
Info: Found entity 1: decode_4r6
Info: Found 1 design units and 1 entities in source file db/mux_kl7.tdf
Info: Found entity 1: mux_kl7
Info: Implemented 102 device resources after synthesis - the final resource count might be different
Info: Implemented 11 input pins
Info: Implemented 10 output pins
Info: Implemented 65 logic cells
Info: Implemented 16 RAM segments
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
Info: Processing ended: Wed Dec 15 03:34:53 2004
Info: Elapsed time: 00:00:05
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