data_buffer.fit.eqn

Altera FPGA CPLD设计高级篇电子书籍

J1_ram_block2a8_PORT_A_data_in = data[0];
J1_ram_block2a8_PORT_A_data_in_reg = DFFE(J1_ram_block2a8_PORT_A_data_in, J1_ram_block2a8_clock_0, , , );
J1_ram_block2a8_PORT_A_address = BUS(H3_safe_q[0], H3_safe_q[1], H3_safe_q[2], H3_safe_q[3], H3_safe_q[4], H3_safe_q[5], H3_safe_q[6], H3_safe_q[7], H3_safe_q[8], H3_safe_q[9], H3_safe_q[10], H3_safe_q[11]);
J1_ram_block2a8_PORT_A_address_reg = DFFE(J1_ram_block2a8_PORT_A_address, J1_ram_block2a8_clock_0, , , );
J1_ram_block2a8_PORT_B_address = BUS(H2_safe_q[0], H2_safe_q[1], H2_safe_q[2], H2_safe_q[3], H2_safe_q[4], H2_safe_q[5], H2_safe_q[6], H2_safe_q[7], H2_safe_q[8], H2_safe_q[9], H2_safe_q[10], H2_safe_q[11]);
J1_ram_block2a8_PORT_B_address_reg = DFFE(J1_ram_block2a8_PORT_B_address, J1_ram_block2a8_clock_1, , , J1_ram_block2a8_clock_enable_1);
J1_ram_block2a8_PORT_A_write_enable = K1L2;
J1_ram_block2a8_PORT_A_write_enable_reg = DFFE(J1_ram_block2a8_PORT_A_write_enable, J1_ram_block2a8_clock_0, , , );
J1_ram_block2a8_PORT_B_read_enable = VCC;
J1_ram_block2a8_PORT_B_read_enable_reg = DFFE(J1_ram_block2a8_PORT_B_read_enable, J1_ram_block2a8_clock_1, , , J1_ram_block2a8_clock_enable_1);
J1_ram_block2a8_clock_0 = GLOBAL(clock);
J1_ram_block2a8_clock_1 = GLOBAL(clock);
J1_ram_block2a8_clock_enable_1 = D1_valid_rreq;
J1_ram_block2a8_PORT_B_data_out = MEMORY(J1_ram_block2a8_PORT_A_data_in_reg, , J1_ram_block2a8_PORT_A_address_reg, J1_ram_block2a8_PORT_B_address_reg, J1_ram_block2a8_PORT_A_write_enable_reg, J1_ram_block2a8_PORT_B_read_enable_reg, , , J1_ram_block2a8_clock_0, J1_ram_block2a8_clock_1, , J1_ram_block2a8_clock_enable_1, , );
J1_ram_block2a8 = J1_ram_block2a8_PORT_B_data_out[0];


--J1_ram_block2a9 is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|ram_block2a9 at M4K_X15_Y13
J1_ram_block2a9_PORT_A_data_in = data[1];
J1_ram_block2a9_PORT_A_data_in_reg = DFFE(J1_ram_block2a9_PORT_A_data_in, J1_ram_block2a9_clock_0, , , );
J1_ram_block2a9_PORT_A_address = BUS(H3_safe_q[0], H3_safe_q[1], H3_safe_q[2], H3_safe_q[3], H3_safe_q[4], H3_safe_q[5], H3_safe_q[6], H3_safe_q[7], H3_safe_q[8], H3_safe_q[9], H3_safe_q[10], H3_safe_q[11]);
J1_ram_block2a9_PORT_A_address_reg = DFFE(J1_ram_block2a9_PORT_A_address, J1_ram_block2a9_clock_0, , , );
J1_ram_block2a9_PORT_B_address = BUS(H2_safe_q[0], H2_safe_q[1], H2_safe_q[2], H2_safe_q[3], H2_safe_q[4], H2_safe_q[5], H2_safe_q[6], H2_safe_q[7], H2_safe_q[8], H2_safe_q[9], H2_safe_q[10], H2_safe_q[11]);
J1_ram_block2a9_PORT_B_address_reg = DFFE(J1_ram_block2a9_PORT_B_address, J1_ram_block2a9_clock_1, , , J1_ram_block2a9_clock_enable_1);
J1_ram_block2a9_PORT_A_write_enable = K1L2;
J1_ram_block2a9_PORT_A_write_enable_reg = DFFE(J1_ram_block2a9_PORT_A_write_enable, J1_ram_block2a9_clock_0, , , );
J1_ram_block2a9_PORT_B_read_enable = VCC;
J1_ram_block2a9_PORT_B_read_enable_reg = DFFE(J1_ram_block2a9_PORT_B_read_enable, J1_ram_block2a9_clock_1, , , J1_ram_block2a9_clock_enable_1);
J1_ram_block2a9_clock_0 = GLOBAL(clock);
J1_ram_block2a9_clock_1 = GLOBAL(clock);
J1_ram_block2a9_clock_enable_1 = D1_valid_rreq;
J1_ram_block2a9_PORT_B_data_out = MEMORY(J1_ram_block2a9_PORT_A_data_in_reg, , J1_ram_block2a9_PORT_A_address_reg, J1_ram_block2a9_PORT_B_address_reg, J1_ram_block2a9_PORT_A_write_enable_reg, J1_ram_block2a9_PORT_B_read_enable_reg, , , J1_ram_block2a9_clock_0, J1_ram_block2a9_clock_1, , J1_ram_block2a9_clock_enable_1, , );
J1_ram_block2a9 = J1_ram_block2a9_PORT_B_data_out[0];


--J1_ram_block2a10 is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|ram_block2a10 at M4K_X15_Y20
J1_ram_block2a10_PORT_A_data_in = data[2];
J1_ram_block2a10_PORT_A_data_in_reg = DFFE(J1_ram_block2a10_PORT_A_data_in, J1_ram_block2a10_clock_0, , , );
J1_ram_block2a10_PORT_A_address = BUS(H3_safe_q[0], H3_safe_q[1], H3_safe_q[2], H3_safe_q[3], H3_safe_q[4], H3_safe_q[5], H3_safe_q[6], H3_safe_q[7], H3_safe_q[8], H3_safe_q[9], H3_safe_q[10], H3_safe_q[11]);
J1_ram_block2a10_PORT_A_address_reg = DFFE(J1_ram_block2a10_PORT_A_address, J1_ram_block2a10_clock_0, , , );
J1_ram_block2a10_PORT_B_address = BUS(H2_safe_q[0], H2_safe_q[1], H2_safe_q[2], H2_safe_q[3], H2_safe_q[4], H2_safe_q[5], H2_safe_q[6], H2_safe_q[7], H2_safe_q[8], H2_safe_q[9], H2_safe_q[10], H2_safe_q[11]);
J1_ram_block2a10_PORT_B_address_reg = DFFE(J1_ram_block2a10_PORT_B_address, J1_ram_block2a10_clock_1, , , J1_ram_block2a10_clock_enable_1);
J1_ram_block2a10_PORT_A_write_enable = K1L2;
J1_ram_block2a10_PORT_A_write_enable_reg = DFFE(J1_ram_block2a10_PORT_A_write_enable, J1_ram_block2a10_clock_0, , , );
J1_ram_block2a10_PORT_B_read_enable = VCC;
J1_ram_block2a10_PORT_B_read_enable_reg = DFFE(J1_ram_block2a10_PORT_B_read_enable, J1_ram_block2a10_clock_1, , , J1_ram_block2a10_clock_enable_1);
J1_ram_block2a10_clock_0 = GLOBAL(clock);
J1_ram_block2a10_clock_1 = GLOBAL(clock);
J1_ram_block2a10_clock_enable_1 = D1_valid_rreq;
J1_ram_block2a10_PORT_B_data_out = MEMORY(J1_ram_block2a10_PORT_A_data_in_reg, , J1_ram_block2a10_PORT_A_address_reg, J1_ram_block2a10_PORT_B_address_reg, J1_ram_block2a10_PORT_A_write_enable_reg, J1_ram_block2a10_PORT_B_read_enable_reg, , , J1_ram_block2a10_clock_0, J1_ram_block2a10_clock_1, , J1_ram_block2a10_clock_enable_1, , );
J1_ram_block2a10 = J1_ram_block2a10_PORT_B_data_out[0];


--J1_ram_block2a11 is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|ram_block2a11 at M4K_X15_Y15
J1_ram_block2a11_PORT_A_data_in = data[3];
J1_ram_block2a11_PORT_A_data_in_reg = DFFE(J1_ram_block2a11_PORT_A_data_in, J1_ram_block2a11_clock_0, , , );
J1_ram_block2a11_PORT_A_address = BUS(H3_safe_q[0], H3_safe_q[1], H3_safe_q[2], H3_safe_q[3], H3_safe_q[4], H3_safe_q[5], H3_safe_q[6], H3_safe_q[7], H3_safe_q[8], H3_safe_q[9], H3_safe_q[10], H3_safe_q[11]);
J1_ram_block2a11_PORT_A_address_reg = DFFE(J1_ram_block2a11_PORT_A_address, J1_ram_block2a11_clock_0, , , );
J1_ram_block2a11_PORT_B_address = BUS(H2_safe_q[0], H2_safe_q[1], H2_safe_q[2], H2_safe_q[3], H2_safe_q[4], H2_safe_q[5], H2_safe_q[6], H2_safe_q[7], H2_safe_q[8], H2_safe_q[9], H2_safe_q[10], H2_safe_q[11]);
J1_ram_block2a11_PORT_B_address_reg = DFFE(J1_ram_block2a11_PORT_B_address, J1_ram_block2a11_clock_1, , , J1_ram_block2a11_clock_enable_1);
J1_ram_block2a11_PORT_A_write_enable = K1L2;
J1_ram_block2a11_PORT_A_write_enable_reg = DFFE(J1_ram_block2a11_PORT_A_write_enable, J1_ram_block2a11_clock_0, , , );
J1_ram_block2a11_PORT_B_read_enable = VCC;
J1_ram_block2a11_PORT_B_read_enable_reg = DFFE(J1_ram_block2a11_PORT_B_read_enable, J1_ram_block2a11_clock_1, , , J1_ram_block2a11_clock_enable_1);
J1_ram_block2a11_clock_0 = GLOBAL(clock);
J1_ram_block2a11_clock_1 = GLOBAL(clock);
J1_ram_block2a11_clock_enable_1 = D1_valid_rreq;
J1_ram_block2a11_PORT_B_data_out = MEMORY(J1_ram_block2a11_PORT_A_data_in_reg, , J1_ram_block2a11_PORT_A_address_reg, J1_ram_block2a11_PORT_B_address_reg, J1_ram_block2a11_PORT_A_write_enable_reg, J1_ram_block2a11_PORT_B_read_enable_reg, , , J1_ram_block2a11_clock_0, J1_ram_block2a11_clock_1, , J1_ram_block2a11_clock_enable_1, , );
J1_ram_block2a11 = J1_ram_block2a11_PORT_B_data_out[0];


--J1_ram_block2a12 is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|ram_block2a12 at M4K_X15_Y23
J1_ram_block2a12_PORT_A_data_in = data[4];
J1_ram_block2a12_PORT_A_data_in_reg = DFFE(J1_ram_block2a12_PORT_A_data_in, J1_ram_block2a12_clock_0, , , );
J1_ram_block2a12_PORT_A_address = BUS(H3_safe_q[0], H3_safe_q[1], H3_safe_q[2], H3_safe_q[3], H3_safe_q[4], H3_safe_q[5], H3_safe_q[6], H3_safe_q[7], H3_safe_q[8], H3_safe_q[9], H3_safe_q[10], H3_safe_q[11]);
J1_ram_block2a12_PORT_A_address_reg = DFFE(J1_ram_block2a12_PORT_A_address, J1_ram_block2a12_clock_0, , , );
J1_ram_block2a12_PORT_B_address = BUS(H2_safe_q[0], H2_safe_q[1], H2_safe_q[2], H2_safe_q[3], H2_safe_q[4], H2_safe_q[5], H2_safe_q[6], H2_safe_q[7], H2_safe_q[8], H2_safe_q[9], H2_safe_q[10], H2_safe_q[11]);
J1_ram_block2a12_PORT_B_address_reg = DFFE(J1_ram_block2a12_PORT_B_address, J1_ram_block2a12_clock_1, , , J1_ram_block2a12_clock_enable_1);
J1_ram_block2a12_PORT_A_write_enable = K1L2;
J1_ram_block2a12_PORT_A_write_enable_reg = DFFE(J1_ram_block2a12_PORT_A_write_enable, J1_ram_block2a12_clock_0, , , );
J1_ram_block2a12_PORT_B_read_enable = VCC;
J1_ram_block2a12_PORT_B_read_enable_reg = DFFE(J1_ram_block2a12_PORT_B_read_enable, J1_ram_block2a12_clock_1, , , J1_ram_block2a12_clock_enable_1);
J1_ram_block2a12_clock_0 = GLOBAL(clock);
J1_ram_block2a12_clock_1 = GLOBAL(clock);
J1_ram_block2a12_clock_enable_1 = D1_valid_rreq;
J1_ram_block2a12_PORT_B_data_out = MEMORY(J1_ram_block2a12_PORT_A_data_in_reg, , J1_ram_block2a12_PORT_A_address_reg, J1_ram_block2a12_PORT_B_address_reg, J1_ram_block2a12_PORT_A_write_enable_reg, J1_ram_block2a12_PORT_B_read_enable_reg, , , J1_ram_block2a12_clock_0, J1_ram_block2a12_clock_1, , J1_ram_block2a12_clock_enable_1, , );
J1_ram_block2a12 = J1_ram_block2a12_PORT_B_data_out[0];


--J1_ram_block2a13 is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|ram_block2a13 at M4K_X15_Y16
J1_ram_block2a13_PORT_A_data_in = data[5];
J1_ram_block2a13_PORT_A_data_in_reg = DFFE(J1_ram_block2a13_PORT_A_data_in, J1_ram_block2a13_clock_0, , , );
J1_ram_block2a13_PORT_A_address = BUS(H3_safe_q[0], H3_safe_q[1], H3_safe_q[2], H3_safe_q[3], H3_safe_q[4], H3_safe_q[5], H3_safe_q[6], H3_safe_q[7], H3_safe_q[8], H3_safe_q[9], H3_safe_q[10], H3_safe_q[11]);
J1_ram_block2a13_PORT_A_address_reg = DFFE(J1_ram_block2a13_PORT_A_address, J1_ram_block2a13_clock_0, , , );
J1_ram_block2a13_PORT_B_address = BUS(H2_safe_q[0], H2_safe_q[1], H2_safe_q[2], H2_safe_q[3], H2_safe_q[4], H2_safe_q[5], H2_safe_q[6], H2_safe_q[7], H2_safe_q[8], H2_safe_q[9], H2_safe_q[10], H2_safe_q[11]);
J1_ram_block2a13_PORT_B_address_reg = DFFE(J1_ram_block2a13_PORT_B_address, J1_ram_block2a13_clock_1, , , J1_ram_block2a13_clock_enable_1);
J1_ram_block2a13_PORT_A_write_enable = K1L2;
J1_ram_block2a13_PORT_A_write_enable_reg = DFFE(J1_ram_block2a13_PORT_A_write_enable, J1_ram_block2a13_clock_0, , , );
J1_ram_block2a13_PORT_B_read_enable = VCC;
J1_ram_block2a13_PORT_B_read_enable_reg = DFFE(J1_ram_block2a13_PORT_B_read_enable, J1_ram_block2a13_clock_1, , , J1_ram_block2a13_clock_enable_1);
J1_ram_block2a13_clock_0 = GLOBAL(clock);
J1_ram_block2a13_clock_1 = GLOBAL(clock);
J1_ram_block2a13_clock_enable_1 = D1_valid_rreq;
J1_ram_block2a13_PORT_B_data_out = MEMORY(J1_ram_block2a13_PORT_A_data_in_reg, , J1_ram_block2a13_PORT_A_address_reg, J1_ram_block2a13_PORT_B_address_reg, J1_ram_block2a13_PORT_A_write_enable_reg, J1_ram_block2a13_PORT_B_read_enable_reg, , , J1_ram_block2a13_clock_0, J1_ram_block2a13_clock_1, , J1_ram_block2a13_clock_enable_1, , );
J1_ram_block2a13 = J1_ram_block2a13_PORT_B_data_out[0];


--J1_ram_block2a14 is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|ram_block2a14 at M4K_X15_Y14
J1_ram_block2a14_PORT_A_data_in = data[6];
J1_ram_block2a14_PORT_A_data_in_reg = DFFE(J1_ram_block2a14_PORT_A_data_in, J1_ram_block2a14_clock_0, , , );
J1_ram_block2a14_PORT_A_address = BUS(H3_safe_q[0], H3_safe_q[1], H3_safe_q[2], H3_safe_q[3], H3_safe_q[4], H3_safe_q[5], H3_safe_q[6], H3_safe_q[7], H3_safe_q[8], H3_safe_q[9], H3_safe_q[10], H3_safe_q[11]);
J1_ram_block2a14_PORT_A_address_reg = DFFE(J1_ram_block2a14_PORT_A_address, J1_ram_block2a14_clock_0, , , );
J1_ram_block2a14_PORT_B_address = BUS(H2_safe_q[0], H2_safe_q[1], H2_safe_q[2], H2_safe_q[3], H2_safe_q[4], H2_safe_q[5], H2_safe_q[6], H2_safe_q[7], H2_safe_q[8], H2_safe_q[9], H2_safe_q[10], H2_safe_q[11]);
J1_ram_block2a14_PORT_B_address_reg = DFFE(J1_ram_block2a14_PORT_B_address, J1_ram_block2a14_clock_1, , , J1_ram_block2a14_clock_enable_1);
J1_ram_block2a14_PORT_A_write_enable = K1L2;
J1_ram_block2a14_PORT_A_write_enable_reg = DFFE(J1_ram_block2a14_PORT_A_write_enable, J1_ram_block2a14_clock_0, , , );
J1_ram_block2a14_PORT_B_read_enable = VCC;
J1_ram_block2a14_PORT_B_read_enable_reg = DFFE(J1_ram_block2a14_PORT_B_read_enable, J1_ram_block2a14_clock_1, , , J1_ram_block2a14_clock_enable_1);
J1_ram_block2a14_clock_0 = GLOBAL(clock);
J1_ram_block2a14_clock_1 = GLOBAL(clock);
J1_ram_block2a14_clock_enable_1 = D1_valid_rreq;
J1_ram_block2a14_PORT_B_data_out = MEMORY(J1_ram_block2a14_PORT_A_data_in_reg, , J1_ram_block2a14_PORT_A_address_reg, J1_ram_block2a14_PORT_B_address_reg, J1_ram_block2a14_PORT_A_write_enable_reg, J1_ram_block2a14_PORT_B_read_enable_reg, , , J1_ram_block2a14_clock_0, J1_ram_block2a14_clock_1, , J1_ram_block2a14_clock_enable_1, , );
J1_ram_block2a14 = J1_ram_block2a14_PORT_B_data_out[0];


--J1_ram_block2a15 is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|ram_block2a15 at M4K_X15_Y27
J1_ram_block2a15_PORT_A_data_in = data[7];
J1_ram_block2a15_PORT_A_data_in_reg = DFFE(J1_ram_block2a15_PORT_A_data_in, J1_ram_block2a15_clock_0, , , );
J1_ram_block2a15_PORT_A_address = BUS(H3_safe_q[0], H3_safe_q[1], H3_safe_q[2], H3_safe_q[3], H3_safe_q[4], H3_safe_q[5], H3_safe_q[6], H3_safe_q[7], H3_safe_q[8], H3_safe_q[9], H3_safe_q[10], H3_safe_q[11]);
J1_ram_block2a15_PORT_A_address_reg = DFFE(J1_ram_block2a15_PORT_A_address, J1_ram_block2a15_clock_0, , , );
J1_ram_block2a15_PORT_B_address = BUS(H2_safe_q[0], H2_safe_q[1], H2_safe_q[2], H2_safe_q[3], H2_safe_q[4], H2_safe_q[5], H2_safe_q[6], H2_safe_q[7], H2_safe_q[8], H2_safe_q[9], H2_safe_q[10], H2_safe_q[11]);
J1_ram_block2a15_PORT_B_address_reg = DFFE(J1_ram_block2a15_PORT_B_address, J1_ram_block2a15_clock_1, , , J1_ram_block2a15_clock_enable_1);
J1_ram_block2a15_PORT_A_write_enable = K1L2;
J1_ram_block2a15_PORT_A_write_enable_reg = DFFE(J1_ram_block2a15_PORT_A_write_enable, J1_ram_block2a15_clock_0, , , );
J1_ram_block2a15_PORT_B_read_enable = VCC;
J1_ram_block2a15_PORT_B_read_enable_reg = DFFE(J1_ram_block2a15_PORT_B_read_enable, J1_ram_block2a15_clock_1, , , J1_ram_block2a15_clock_enable_1);
J1_ram_block2a15_clock_0 = GLOBAL(clock);
J1_ram_block2a15_clock_1 = GLOBAL(clock);
J1_ram_block2a15_clock_enable_1 = D1_valid_rreq;
J1_ram_block2a15_PORT_B_data_out = MEMORY(J1_ram_block2a15_PORT_A_data_in_reg, , J1_ram_block2a15_PORT_A_address_reg, J1_ram_block2a15_PORT_B_address_reg, J1_ram_block2a15_PORT_A_write_enable_reg, J1_ram_block2a15_PORT_B_read_enable_reg, , , J1_ram_block2a15_clock_0, J1_ram_block2a15_clock_1, , J1_ram_block2a15_clock_enable_1, , );
J1_ram_block2a15 = J1_ram_block2a15_PORT_B_data_out[0];


--H1_safe_q[12] is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|lpm_counter:count_usedw|alt_counter_stratix:wysi_counter|safe_q[12] at LC_X17_Y18_N6
--operation mode is normal

H1_safe_q[12]_carry_eqn = (!H1L32 & H1L65) # (H1L32 & H1L75);
H1_safe_q[12]_lut_out = H1_safe_q[12]_carry_eqn $ !H1_safe_q[12];
H1_safe_q[12] = DFFEA(H1_safe_q[12]_lut_out, GLOBAL(clock), VCC, , E1L1, , );


--H1_safe_q[11] is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|lpm_counter:count_usedw|alt_counter_stratix:wysi_counter|safe_q[11] at LC_X17_Y18_N5
--operation mode is arithmetic

H1_safe_q[11]_carry_eqn = H1L32;
H1_safe_q[11]_lut_out = H1_safe_q[11] $ H1_safe_q[11]_carry_eqn;
H1_safe_q[11] = DFFEA(H1_safe_q[11]_lut_out, GLOBAL(clock), VCC, , E1L1, , );

--H1L65 is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|lpm_counter:count_usedw|alt_counter_stratix:wysi_counter|safe_q[11]~COUT0 at LC_X17_Y18_N5
--operation mode is arithmetic

H1L65_cout_0 = H1_safe_q[11] $ D1_valid_wreq # !H1L32;
H1L65 = CARRY(H1L65_cout_0);

--H1L75 is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|lpm_counter:count_usedw|alt_counter_stratix:wysi_counter|safe_q[11]~COUT1 at LC_X17_Y18_N5
--operation mode is arithmetic

H1L75_cout_1 = H1_safe_q[11] $ D1_valid_wreq # !H1L32;
H1L75 = CARRY(H1L75_cout_1);


--H1_safe_q[10] is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|lpm_counter:count_usedw|alt_counter_stratix:wysi_counter|safe_q[10] at LC_X17_Y18_N4
--operation mode is arithmetic

H1_safe_q[10]_carry_eqn = (!H1L31 & H1L25) # (H1L31 & H1L35);
H1_safe_q[10]_lut_out = H1_safe_q[10] $ !H1_safe_q[10]_carry_eqn;
H1_safe_q[10] = DFFEA(H1_safe_q[10]_lut_out, GLOBAL(clock), VCC, , E1L1, , );

--H1L32 is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|lpm_counter:count_usedw|alt_counter_stratix:wysi_counter|counter_cell[10]~COUT at LC_X17_Y18_N4
--operation mode is arithmetic

H1L32 = CARRY(!H1L35 & (H1_safe_q[10] $ !D1_valid_wreq));


--H1_safe_q[9] is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|lpm_counter:count_usedw|alt_counter_stratix:wysi_counter|safe_q[9] at LC_X17_Y18_N3
--operation mode is arithmetic

H1_safe_q[9]_carry_eqn = (!H1L31 & H1L94) # (H1L31 & H1L05);
H1_safe_q[9]_lut_out = H1_safe_q[9] $ H1_safe_q[9]_carry_eqn;
H1_safe_q[9] = DFFEA(H1_safe_q[9]_lut_out, GLOBAL(clock), VCC, , E1L1, , );

--H1L25 is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|lpm_counter:count_usedw|alt_counter_stratix:wysi_counter|safe_q[9]~COUT0 at LC_X17_Y18_N3
--operation mode is arithmetic

H1L25_cout_0 = H1_safe_q[9] $ D1_valid_wreq # !H1L94;
H1L25 = CARRY(H1L25_cout_0);

--H1L35 is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|lpm_counter:count_usedw|alt_counter_stratix:wysi_counter|safe_q[9]~COUT1 at LC_X17_Y18_N3
--operation mode is arithmetic