data_buffer.map.eqn

Altera FPGA CPLD设计高级篇电子书籍

L1L6 = J1_ram_block2a13 & (J1_ram_block2a5 # J1_address_reg_b[0]) # !J1_ram_block2a13 & J1_ram_block2a5 & !J1_address_reg_b[0];


--L1L5 is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|mux_kl7:mux4|w_result363w~10
--operation mode is normal

L1L5 = J1_ram_block2a12 & (J1_ram_block2a4 # J1_address_reg_b[0]) # !J1_ram_block2a12 & J1_ram_block2a4 & !J1_address_reg_b[0];


--L1L4 is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|mux_kl7:mux4|w_result351w~10
--operation mode is normal

L1L4 = J1_ram_block2a11 & (J1_ram_block2a3 # J1_address_reg_b[0]) # !J1_ram_block2a11 & J1_ram_block2a3 & !J1_address_reg_b[0];


--L1L3 is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|mux_kl7:mux4|w_result339w~10
--operation mode is normal

L1L3 = J1_ram_block2a10 & (J1_ram_block2a2 # J1_address_reg_b[0]) # !J1_ram_block2a10 & J1_ram_block2a2 & !J1_address_reg_b[0];


--L1L2 is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|mux_kl7:mux4|w_result327w~10
--operation mode is normal

L1L2 = J1_ram_block2a9 & (J1_ram_block2a1 # J1_address_reg_b[0]) # !J1_ram_block2a9 & J1_ram_block2a1 & !J1_address_reg_b[0];


--L1L1 is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|mux_kl7:mux4|w_result313w~10
--operation mode is normal

L1L1 = J1_ram_block2a8 & (J1_ram_block2a0 # J1_address_reg_b[0]) # !J1_ram_block2a8 & J1_ram_block2a0 & !J1_address_reg_b[0];


--E1_b_full is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|b_full
--operation mode is normal

E1_b_full_lut_out = E1L7 # E1_b_full & !rdreq;
E1_b_full = DFFEA(E1_b_full_lut_out, clock, VCC, , , , );


--E1_b_non_empty is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|b_non_empty
--operation mode is normal

E1_b_non_empty_lut_out = E1_b_full # wrreq # E1_b_non_empty & E1L31;
E1_b_non_empty = DFFEA(E1_b_non_empty_lut_out, clock, VCC, , , , );


--D1_valid_wreq is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|valid_wreq
--operation mode is normal

D1_valid_wreq = wrreq & !E1_b_full;


--D1_valid_rreq is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|valid_rreq
--operation mode is normal

D1_valid_rreq = E1_b_non_empty & rdreq;


--E1L3 is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|b_full~128
--operation mode is normal

E1L3 = H1_safe_q[3] & H1_safe_q[2] & H1_safe_q[1] & H1_safe_q[0];


--E1L4 is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|b_full~129
--operation mode is normal

E1L4 = H1_safe_q[7] & H1_safe_q[6] & H1_safe_q[5] & H1_safe_q[4];


--E1L5 is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|b_full~130
--operation mode is normal

E1L5 = H1_safe_q[11] & H1_safe_q[10] & H1_safe_q[9] & H1_safe_q[8];


--E1L6 is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|b_full~131
--operation mode is normal

E1L6 = H1_safe_q[12] & E1_b_non_empty & wrreq & !rdreq;


--E1L7 is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|b_full~132
--operation mode is normal

E1L7 = E1L3 & E1L4 & E1L5 & E1L6;


--E1L9 is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|b_non_empty~148
--operation mode is normal

E1L9 = H1_safe_q[1] # !H1_safe_q[0];


--E1L01 is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|b_non_empty~149
--operation mode is normal

E1L01 = H1_safe_q[5] # H1_safe_q[4] # H1_safe_q[3] # H1_safe_q[2];


--E1L11 is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|b_non_empty~150
--operation mode is normal

E1L11 = H1_safe_q[9] # H1_safe_q[8] # H1_safe_q[7] # H1_safe_q[6];


--E1L21 is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|b_non_empty~151
--operation mode is normal

E1L21 = H1_safe_q[12] # H1_safe_q[11] # H1_safe_q[10] # !rdreq;


--E1L31 is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|b_non_empty~152
--operation mode is normal

E1L31 = E1L9 # E1L01 # E1L11 # E1L21;


--K1L2 is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|decode_4r6:decode3|eq_node[1]~19
--operation mode is normal

K1L2 = wrreq & !E1_b_full & H3_safe_q[12];


--K1L1 is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|decode_4r6:decode3|eq_node[0]~21
--operation mode is normal

K1L1 = wrreq & !E1_b_full & !H3_safe_q[12];


--E1L1 is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|_~68
--operation mode is normal

E1L1 = E1_b_non_empty & (rdreq $ (wrreq & !E1_b_full)) # !E1_b_non_empty & wrreq & !E1_b_full;


--wrreq is wrreq
--operation mode is input

wrreq = INPUT();


--clock is clock
--operation mode is input

clock = INPUT();


--rdreq is rdreq
--operation mode is input

rdreq = INPUT();


--data[7] is data[7]
--operation mode is input

data[7] = INPUT();


--data[6] is data[6]
--operation mode is input

data[6] = INPUT();


--data[5] is data[5]
--operation mode is input

data[5] = INPUT();


--data[4] is data[4]
--operation mode is input

data[4] = INPUT();


--data[3] is data[3]
--operation mode is input

data[3] = INPUT();


--data[2] is data[2]
--operation mode is input

data[2] = INPUT();


--data[1] is data[1]
--operation mode is input

data[1] = INPUT();


--data[0] is data[0]
--operation mode is input

data[0] = INPUT();


--q[7] is q[7]
--operation mode is output

q[7] = OUTPUT(L1L8);


--q[6] is q[6]
--operation mode is output

q[6] = OUTPUT(L1L7);


--q[5] is q[5]
--operation mode is output

q[5] = OUTPUT(L1L6);


--q[4] is q[4]
--operation mode is output

q[4] = OUTPUT(L1L5);


--q[3] is q[3]
--operation mode is output

q[3] = OUTPUT(L1L4);


--q[2] is q[2]
--operation mode is output

q[2] = OUTPUT(L1L3);


--q[1] is q[1]
--operation mode is output

q[1] = OUTPUT(L1L2);


--q[0] is q[0]
--operation mode is output

q[0] = OUTPUT(L1L1);


--full is full
--operation mode is output

full = OUTPUT(E1_b_full);


--empty is empty
--operation mode is output

empty = OUTPUT(!E1_b_non_empty);