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<A HREF=inst.html></A> <A HREF=ydir.html></A> <A HREF=inde.html></A> <A HREF=zarch.html></A> <A HREF=zioreg.html></A> <A HREF=yexp.html></A> <A HREF=zzdatas.html></A> <!-- text used in the movie-->
<!--GPR   All the register operating instructions in the instruction set have direct and  single-cycle access to all registers.    The only exception is the five constant arithmetic and logic instructions  SBCI, SUBI, CPI, ANDI, ORI between a constant and a register and the LDI instruction for load immediate constant data. These instructions apply to the  second half of the registers in the Register File (R16..R31).    The general SBC, SUB, CP, AND, OR  and all other operations between two  registers or on a single register apply to the entire Register File.   As shown in Figure , each register is also assigned a data memory address,  mapping them directly into the first 32 locations of the user Data Space.   Although the Register File is not physically implemented as SRAM locations,  this memory organization provides great flexibility in access of the registers,  as the X-, Y-, and Z-registers can be set to index any register in the file. General Purpose Registers R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R18 R19 R20 R21 R22 R23 R17 R24 R25 R26 R27 R28 R29 R30 R31 Z-register High Byte Z-register Low Byte Y-register High Byte Y-register Low Byte X-register High Byte X-register Low Byte $10 $12 $13 $14 $15 $16 $17 $11 $18 $19 $1A $1B $1C $1D $1E $1F $00 $02 $03 $04 $05 $06 $07 $01 $08 $09 $0A $0B $0C $0D $0E $0F The CPU contains 32 x 8-bit  general purpose registers with a single clock cycle  access time. All the 32 registers  are directly connected to  the Arithmetic Logic Unit (ALU),  allowing two independent  registers to be accessed  in one single instruction  executed in one clock cycle. --><OBJECT classid="clsid:D27CDB6E-AE6D-11cf-96B8-444553540000"
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